il_wr
il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
il_wr(il, FH39_CBCC_BASE(txq_id), 0);
il_wr(il, FH39_TCSR_CONFIG(txq_id),
il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
il_wr(il, FH39_RCSR_WPTR(0), 0);
il_wr(il, FH39_RCSR_CONFIG(0),
il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
il_wr(il, FH39_TSSR_MSG_CONFIG,
il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
il_wr(il, HBUS_TARG_MBX_C,
il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
il_wr(il, FH49_TX_CHICKEN_BITS_REG,
il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
il_wr(il, HBUS_TARG_MEM_RADDR, i + IL4965_RTC_INST_LOWER_BOUND);
il_wr(il, HBUS_TARG_MEM_RADDR, IL4965_RTC_INST_LOWER_BOUND);
il_wr(il, rx_wrt_ptr_reg, q->write_actual);
il_wr(il, rx_wrt_ptr_reg, q->write_actual);
il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));