iic
tsunami_64 iic; /* a.k.a. iic0 */
volatile struct iic_regs __iomem *iic = dev->vaddr;
out_8(&iic->lmadr, 0);
out_8(&iic->hmadr, 0);
out_8(&iic->lsadr, 0);
out_8(&iic->hsadr, 0);
out_8(&iic->sts, STS_SCMP | STS_IRQA);
out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
out_8(&iic->clkdiv, dev->clckdiv);
out_8(&iic->xfrcnt, 0);
out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
out_8(&iic->cntl, 0);
out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
volatile struct iic_regs __iomem *iic = dev->vaddr;
out_8(&iic->xtcntlss, XTCNTLSS_SRST);
dc = in_8(&iic->directcntl);
out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
dc = in_8(&iic->directcntl);
out_8(&iic->directcntl, dc);
out_8(&iic->directcntl, dc);
out_8(&iic->xtcntlss, 0);
static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
while ((in_8(&iic->directcntl) & mask) != mask){
volatile struct iic_regs __iomem *iic = dev->vaddr;
out_8(&iic->xtcntlss, XTCNTLSS_SRST);
out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
out_8(&iic->directcntl, DIRCNTL_SCC);
out_8(&iic->directcntl, sda);
out_8(&iic->directcntl, sda);
out_8(&iic->directcntl, DIRCNTL_SCC | sda);
if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
out_8(&iic->directcntl, sda);
out_8(&iic->directcntl, DIRCNTL_SDAC);
out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
out_8(&iic->directcntl, 0);
out_8(&iic->directcntl, DIRCNTL_SCC);
if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
out_8(&iic->xtcntlss, 0);
volatile struct iic_regs __iomem *iic = dev->vaddr;
dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
out_8(&iic->sts, STS_IRQA | STS_SCMP);
volatile struct iic_regs __iomem *iic = dev->vaddr;
if (unlikely(in_8(&iic->sts) & STS_ERR)){
in_8(&iic->extsts));
out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
volatile struct iic_regs __iomem *iic = dev->vaddr;
out_8(&iic->cntl, CNTL_HMT);
while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
volatile struct iic_regs __iomem *iic = dev->vaddr;
!(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
else if (unlikely(in_8(&iic->sts) & STS_PT)){
while (in_8(&iic->sts) & STS_PT){
volatile struct iic_regs __iomem *iic = dev->vaddr;
u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
out_8((void __iomem *)&iic->mdbuf, *buf++);
out_8(&iic->cntl, cmd);
*buf++ = in_8((void __iomem *)&iic->mdbuf);
volatile struct iic_regs __iomem *iic = dev->vaddr;
out_8(&iic->cntl, CNTL_AMD);
out_8(&iic->lmadr, i2c_10bit_addr_lo_from_msg(msg));
out_8(&iic->hmadr, i2c_10bit_addr_hi_from_msg(msg) & ~I2C_M_RD);
out_8(&iic->cntl, 0);
out_8(&iic->lmadr, i2c_8bit_addr_from_msg(msg) & ~I2C_M_RD);
volatile struct iic_regs __iomem *iic = dev->vaddr;
if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
volatile struct iic_regs __iomem *iic = dev->vaddr;
in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
in_8(&iic->xtcntlss), in_8(&iic->directcntl));
struct sm501_platdata_gpio_i2c *iic)
GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH",
iic->pin_sda % 32, NULL, 0,
GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH",
iic->pin_scl % 32, NULL, 1,
icd->timeout = iic->timeout;
icd->udelay = iic->udelay;
pdev->id = iic->bus_num;
iic->bus_num,
iic->pin_sda, iic->pin_scl);
struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
ret = sm501_register_gpio_i2c_instance(sm, iic);