Symbol: igcsr32
arch/alpha/include/asm/core_irongate.h
100
igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */
arch/alpha/include/asm/core_irongate.h
101
igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */
arch/alpha/include/asm/core_irongate.h
102
igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */
arch/alpha/include/asm/core_irongate.h
103
igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */
arch/alpha/include/asm/core_irongate.h
104
igcsr32 io_baselim; /* 0x30 - IO base, IO limit */
arch/alpha/include/asm/core_irongate.h
105
igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */
arch/alpha/include/asm/core_irongate.h
106
igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */
arch/alpha/include/asm/core_irongate.h
110
extern igcsr32 *IronECC;
arch/alpha/include/asm/core_irongate.h
38
igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
arch/alpha/include/asm/core_irongate.h
39
igcsr32 stat_cmd; /* 0x04 - status, command */
arch/alpha/include/asm/core_irongate.h
40
igcsr32 class; /* 0x08 - class code, rev ID */
arch/alpha/include/asm/core_irongate.h
41
igcsr32 latency; /* 0x0C - header type, PCI latency */
arch/alpha/include/asm/core_irongate.h
42
igcsr32 bar0; /* 0x10 - BAR0 - AGP */
arch/alpha/include/asm/core_irongate.h
43
igcsr32 bar1; /* 0x14 - BAR1 - GART */
arch/alpha/include/asm/core_irongate.h
44
igcsr32 bar2; /* 0x18 - Power Management reg block */
arch/alpha/include/asm/core_irongate.h
46
igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */
arch/alpha/include/asm/core_irongate.h
48
igcsr32 capptr; /* 0x34 - Capabilities pointer */
arch/alpha/include/asm/core_irongate.h
50
igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */
arch/alpha/include/asm/core_irongate.h
52
igcsr32 bacsr10; /* 0x40 - base address chip selects */
arch/alpha/include/asm/core_irongate.h
53
igcsr32 bacsr32; /* 0x44 - base address chip selects */
arch/alpha/include/asm/core_irongate.h
54
igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects
arch/alpha/include/asm/core_irongate.h
57
igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */
arch/alpha/include/asm/core_irongate.h
59
igcsr32 drammap; /* 0x50 - address mapping control */
arch/alpha/include/asm/core_irongate.h
60
igcsr32 dramtm; /* 0x54 - timing, driver strength */
arch/alpha/include/asm/core_irongate.h
61
igcsr32 dramms; /* 0x58 - DRAM mode/status */
arch/alpha/include/asm/core_irongate.h
63
igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */
arch/alpha/include/asm/core_irongate.h
65
igcsr32 biu0; /* 0x60 - bus interface unit */
arch/alpha/include/asm/core_irongate.h
66
igcsr32 biusip; /* 0x64 - Serial initialisation pkt */
arch/alpha/include/asm/core_irongate.h
68
igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */
arch/alpha/include/asm/core_irongate.h
70
igcsr32 mro; /* 0x70 - memory request optimiser */
arch/alpha/include/asm/core_irongate.h
72
igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */
arch/alpha/include/asm/core_irongate.h
74
igcsr32 whami; /* 0x80 - who am I */
arch/alpha/include/asm/core_irongate.h
75
igcsr32 pciarb; /* 0x84 - PCI arbitration control */
arch/alpha/include/asm/core_irongate.h
76
igcsr32 pcicfg; /* 0x88 - PCI config status */
arch/alpha/include/asm/core_irongate.h
78
igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */
arch/alpha/include/asm/core_irongate.h
80
igcsr32 pci_mem; /* 0x9C - PCI top of memory,
arch/alpha/include/asm/core_irongate.h
84
igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */
arch/alpha/include/asm/core_irongate.h
85
igcsr32 agpstat; /* 0xA4 - AGP status register */
arch/alpha/include/asm/core_irongate.h
86
igcsr32 agpcmd; /* 0xA8 - AGP control register */
arch/alpha/include/asm/core_irongate.h
87
igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */
arch/alpha/include/asm/core_irongate.h
88
igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
arch/alpha/include/asm/core_irongate.h
94
igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */
arch/alpha/include/asm/core_irongate.h
95
igcsr32 stat_cmd; /* 0x04 - Status and Command regs */
arch/alpha/include/asm/core_irongate.h
96
igcsr32 class; /* 0x08 - subclass, baseclass etc */
arch/alpha/include/asm/core_irongate.h
97
igcsr32 htype; /* 0x0C - header type (at 0x0E) */
arch/alpha/include/asm/core_irongate.h
98
igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */
arch/alpha/include/asm/core_irongate.h
99
igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */
arch/alpha/kernel/core_irongate.c
44
igcsr32 *IronECC;