CLK_CFG_UPDATE2
16, 2, 23, CLK_CFG_UPDATE2, TOP_MUX_TL_SHIFT,
24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_TL_P1_SHIFT,
0, 2, 7, CLK_CFG_UPDATE2, TOP_MUX_TL_P2_SHIFT,
CLK_CFG_UPDATE2, TOP_MUX_EMI_INTERFACE_546_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SDF_SHIFT),
24, 2, 31, CLK_CFG_UPDATE2, TOP_MUX_UARTHUB_BCLK_SHIFT,
CLK_CFG_UPDATE2, TOP_MUX_DPSW_CMP_26M_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SMAPCK_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SSR_PKA_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SSR_DMA_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SSR_KDF_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SSR_RNG_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SPU0_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_SPU1_SHIFT),
CLK_CFG_UPDATE2, TOP_MUX_DXCC_SHIFT),