drivers/gpu/drm/i915/display/i9xx_plane.c

699

i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

drivers/gpu/drm/i915/display/intel_display_irq.c

1666

i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1708

i915_enable_pipestat(display, pipe,

drivers/gpu/drm/i915/display/intel_display_irq.c

2008

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2009

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2022

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2023

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2024

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2087

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2089

i915_enable_pipestat(display, pipe, pipestat_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

412

i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

414

i915_enable_pipestat(display, PIPE_A,

drivers/gpu/drm/i915/display/intel_display_irq.h

75

void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

drivers/gpu/drm/i915/display/intel_tv.c

1670

i915_enable_pipestat(display, 0,