idtcm_write
err = idtcm_write(idtcm, RESET_CTRL,
err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
err = idtcm_write(idtcm, channel->dpll_n,
err = idtcm_write(idtcm, channel->dpll_ctrl_n,
err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
err = idtcm_write(idtcm, channel->tod_read_secondary,
err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
err = idtcm_write(idtcm, channel->tod_read_primary,
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
err = idtcm_write(idtcm, channel->hw_dpll_n,
err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
err = idtcm_write(idtcm, channel->hw_dpll_n,
err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
err = idtcm_write(idtcm, channel->hw_dpll_n,