CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0),