arch/mips/kernel/elf.c

267

static inline void set_thread_fp_mode(int hybrid, int regs32)

arch/mips/kernel/elf.c

269

if (hybrid)

arch/x86/events/core.c

1165

union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);

arch/x86/events/core.c

1573

cntr_mask = hybrid(cpuc->pmu, cntr_mask);

arch/x86/events/core.c

1574

fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);

arch/x86/events/core.c

1575

pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);

arch/x86/events/core.c

1650

union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);

arch/x86/events/core.c

173

struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);

arch/x86/events/core.c

2125

pr_info("... generic bitmap: %016llx\n", hybrid(pmu, cntr_mask64));

arch/x86/events/core.c

2127

pr_info("... fixed-purpose bitmap: %016llx\n", hybrid(pmu, fixed_cntr_mask64));

arch/x86/events/core.c

2130

pr_info("... global_ctrl mask: %016llx\n", hybrid(pmu, intel_ctrl));

arch/x86/events/core.c

2563

if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mask)))

arch/x86/events/core.c

569

if (hybrid(pmu, arch_pebs_cap).pdists)

arch/x86/events/intel/core.c

2780

u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);

arch/x86/events/intel/core.c

3460

struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap);

arch/x86/events/intel/core.c

3701

unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);

arch/x86/events/intel/core.c

3702

unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);

arch/x86/events/intel/core.c

3880

status &= hybrid(cpuc->pmu, intel_ctrl);

arch/x86/events/intel/core.c

4048

struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);

arch/x86/events/intel/core.c

4083

struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);

arch/x86/events/intel/core.c

4243

struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);

arch/x86/events/intel/core.c

4780

union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);

arch/x86/events/intel/core.c

4866

return !!hybrid(pmu, acr_cause_mask64);

arch/x86/events/intel/core.c

4889

caps = hybrid(pmu, arch_pebs_cap).caps;

arch/x86/events/intel/core.c

4899

event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64);

arch/x86/events/intel/core.c

4908

event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64);

arch/x86/events/intel/core.c

4942

struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);

arch/x86/events/intel/core.c

4959

u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &

arch/x86/events/intel/core.c

5128

if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||

arch/x86/events/intel/core.c

5129

num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))

arch/x86/events/intel/core.c

5280

u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);

arch/x86/events/intel/core.c

5785

u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;

arch/x86/events/intel/core.c

5821

mask = hybrid(dev_get_drvdata(dev), config_mask);

arch/x86/events/intel/core.c

5827

union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);

arch/x86/events/intel/core.c

6094

mask = hybrid(pmu, acr_cntr_mask64) & gp_mask;

arch/x86/events/intel/core.c

6097

if (hybrid(pmu, acr_cntr_mask64) ==

arch/x86/events/intel/core.c

6098

hybrid(pmu, acr_cause_mask64))

arch/x86/events/intel/core.c

6100

mask = hybrid(pmu, acr_cause_mask64) & gp_mask;

arch/x86/events/intel/core.c

6104

mask = hybrid(pmu, arch_pebs_cap).counters &

arch/x86/events/intel/core.c

6110

mask = hybrid(pmu, arch_pebs_cap).pdists &

arch/x86/events/intel/core.c

6125

struct event_constraint *event_constraints = hybrid(pmu, event_constraints);

arch/x86/events/intel/core.c

6126

struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints);

arch/x86/events/intel/core.c

6127

u64 cntr_mask = hybrid(pmu, cntr_mask64);

arch/x86/events/intel/core.c

6128

u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64);

arch/x86/events/intel/core.c

6129

u64 intel_ctrl = hybrid(pmu, intel_ctrl);

arch/x86/events/intel/core.c

6157

if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM)

arch/x86/events/intel/core.c

6163

u64 caps = hybrid(pmu, arch_pebs_cap).caps;

arch/x86/events/intel/core.c

6193

hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;

arch/x86/events/intel/core.c

6195

hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;

arch/x86/events/intel/core.c

6197

hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;

arch/x86/events/intel/core.c

6202

hybrid(pmu, cntr_mask64) = eax;

arch/x86/events/intel/core.c

6203

hybrid(pmu, fixed_cntr_mask64) = ebx;

arch/x86/events/intel/core.c

6211

hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx);

arch/x86/events/intel/core.c

6213

hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx);

arch/x86/events/intel/core.c

6220

hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;

arch/x86/events/intel/core.c

6226

hybrid(pmu, arch_pebs_cap).counters = pebs_mask;

arch/x86/events/intel/core.c

6227

hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;

arch/x86/events/intel/core.c

6242

rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities);

arch/x86/events/intel/core.c

7740

hybrid(pmu, event_constraints) = intel_glc_event_constraints;

arch/x86/events/intel/core.c

7741

hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;

arch/x86/events/intel/core.c

7769

hybrid(pmu, event_constraints) = intel_grt_event_constraints;

arch/x86/events/intel/core.c

7770

hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;

arch/x86/events/intel/core.c

7771

hybrid(pmu, extra_regs) = intel_grt_extra_regs;

arch/x86/events/intel/core.c

7781

hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints;

arch/x86/events/intel/core.c

7782

hybrid(pmu, extra_regs) = intel_cmt_extra_regs;

arch/x86/events/intel/core.c

7788

hybrid(pmu, event_constraints) = intel_lnc_event_constraints;

arch/x86/events/intel/core.c

7789

hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;

arch/x86/events/intel/core.c

7790

hybrid(pmu, extra_regs) = intel_lnc_extra_regs;

arch/x86/events/intel/core.c

7805

hybrid(pmu, event_constraints) = intel_pnc_event_constraints;

arch/x86/events/intel/core.c

7806

hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;

arch/x86/events/intel/core.c

7807

hybrid(pmu, extra_regs) = intel_pnc_extra_regs;

arch/x86/events/intel/core.c

7821

hybrid(pmu, event_constraints) = intel_skt_event_constraints;

arch/x86/events/intel/core.c

7831

hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;

arch/x86/events/intel/core.c

7853

hybrid(pmu, event_constraints) = intel_arw_event_constraints;

arch/x86/events/intel/core.c

7854

hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;

arch/x86/events/intel/core.c

7855

hybrid(pmu, extra_regs) = intel_arw_extra_regs;

arch/x86/events/intel/ds.c

1562

struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);

arch/x86/events/intel/ds.c

3205

mask = hybrid(cpuc->pmu, pebs_events_mask) |

arch/x86/events/intel/ds.c

3206

(hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);

arch/x86/events/intel/ds.c

3266

mask = hybrid(cpuc->pmu, arch_pebs_cap).counters & cpuc->pebs_enabled;

arch/x86/events/perf_event.h

1321

return hweight64(hybrid(pmu, cntr_mask64));

arch/x86/events/perf_event.h

1326

return fls64(hybrid(pmu, cntr_mask64));

arch/x86/events/perf_event.h

1331

return hweight64(hybrid(pmu, fixed_cntr_mask64));

arch/x86/events/perf_event.h

1336

return fls64(hybrid(pmu, fixed_cntr_mask64));

arch/x86/events/perf_event.h

1341

return event->attr.config & hybrid(event->pmu, config_mask);

arch/x86/events/perf_event.h

1346

return !!(hybrid(pmu, config_mask) &

arch/x86/events/perf_event.h

1460

u64 intel_ctrl = hybrid(pmu, intel_ctrl);

arch/x86/events/perf_event.h

1863

return fls((u32)hybrid(pmu, pebs_events_mask));

drivers/md/dm-table.c

901

unsigned int bio_based = 0, request_based = 0, hybrid = 0;

drivers/md/dm-table.c

919

hybrid = 1;

drivers/md/dm-table.c

931

if (hybrid && !bio_based && !request_based) {

tools/perf/arch/x86/tests/arch-tests.c

27

TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"),