drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

100

hwsq_cmd(hwsq, 3, (u8[]){ 0x42, data, data >> 8 });

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

104

if ((addr & 0xffff0000) != (hwsq->addr & 0xffff0000)) {

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

105

hwsq_cmd(hwsq, 5, (u8[]){ 0xe0, addr, addr >> 8,

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

108

hwsq_cmd(hwsq, 3, (u8[]){ 0x40, addr, addr >> 8 });

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

111

hwsq->addr = addr;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

112

hwsq->data = data;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

116

nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

118

nvkm_debug(hwsq->subdev, " FLAG[%02x] = %d\n", flag, data);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

124

hwsq_cmd(hwsq, 1, (u8[]){ flag });

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

128

nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

130

nvkm_debug(hwsq->subdev, " WAIT[%02x] = %d\n", flag, data);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

131

hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

135

nvkm_hwsq_wait_vblank(struct nvkm_hwsq *hwsq)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

137

struct nvkm_subdev *subdev = hwsq->subdev;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

162

nvkm_hwsq_wait(hwsq, head_sync ? 0x3 : 0x1, 0x0);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

163

nvkm_hwsq_wait(hwsq, head_sync ? 0x3 : 0x1, 0x1);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

167

nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

175

nvkm_debug(hwsq->subdev, " DELAY = %d ns\n", nsec);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

176

hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

37

hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[])

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

39

memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

40

hwsq->c.size += size;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

46

struct nvkm_hwsq *hwsq;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

48

hwsq = *phwsq = kmalloc_obj(*hwsq);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

49

if (hwsq) {

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

50

hwsq->subdev = subdev;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

51

hwsq->addr = ~0;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

52

hwsq->data = ~0;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

53

memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

54

hwsq->c.size = 0;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

57

return hwsq ? 0 : -ENOMEM;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

63

struct nvkm_hwsq *hwsq = *phwsq;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

65

if (hwsq) {

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

66

struct nvkm_subdev *subdev = hwsq->subdev;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

68

hwsq->c.size = (hwsq->c.size + 4) / 4;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

69

if (hwsq->c.size <= bus->func->hwsq_size) {

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

72

(u32 *)hwsq->c.data,

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

73

hwsq->c.size);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

81

for (i = 0; ret && i < hwsq->c.size; i++)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

82

nvkm_error(subdev, "\t%08x\n", ((u32 *)hwsq->c.data)[i]);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

85

kfree(hwsq);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

91

nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

93

nvkm_debug(hwsq->subdev, "R[%06x] = %08x\n", addr, data);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

95

if (hwsq->data != data) {

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

96

if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

97

hwsq_cmd(hwsq, 5, (u8[]){ 0xe2, data, data >> 8,

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

104

nvkm_hwsq_wr32(ram->hwsq, reg->addr+off, reg->data);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

111

hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

117

hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

126

hwsq_setf(struct hwsq *ram, u8 flag, int data)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

128

nvkm_hwsq_setf(ram->hwsq, flag, data);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

132

hwsq_wait(struct hwsq *ram, u8 flag, u8 data)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

134

nvkm_hwsq_wait(ram->hwsq, flag, data);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

138

hwsq_wait_vblank(struct hwsq *ram)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

140

nvkm_hwsq_wait_vblank(ram->hwsq);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

144

hwsq_nsec(struct hwsq *ram, u32 nsec)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

146

nvkm_hwsq_nsec(ram->hwsq, nsec);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

61

hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

65

ret = nvkm_hwsq_init(subdev, &ram->hwsq);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

75

hwsq_exec(struct hwsq *ram, bool exec)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

79

ret = nvkm_hwsq_fini(&ram->hwsq, exec);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

8

struct nvkm_hwsq *hwsq;

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

86

hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

95

hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

372

struct nv50_clk_hwsq *hwsq = &clk->hwsq;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

385

out = clk_init(hwsq, subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

389

clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

390

clk_nsec(hwsq, 8000);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

391

clk_setf(hwsq, 0x10, 0x00); /* disable fb */

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

392

clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

447

clk_mask(hwsq, mast, mastm, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

448

clk_mask(hwsq, divs, divsm, divsv);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

449

clk_mask(hwsq, mast, mastm, mastv);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

455

clk_mask(hwsq, mast, 0x001000b0, 0x00100080);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

457

clk_mask(hwsq, mast, 0x000000b3, 0x00000081);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

464

clk_mask(hwsq, nvpll[0], 0xc03f0100,

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

466

clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

475

clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

476

clk_mask(hwsq, mast, 0x00100033, 0x00000023);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

482

clk_mask(hwsq, spll[0], 0xc03f0100,

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

484

clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

485

clk_mask(hwsq, mast, 0x00100033, 0x00000033);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

489

clk_setf(hwsq, 0x10, 0x01); /* enable fb */

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

490

clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

491

clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

499

return clk_exec(&clk->hwsq, true);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

506

clk_exec(&clk->hwsq, false);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

523

clk->hwsq.r_fifo = hwsq_reg(0x002504);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

524

clk->hwsq.r_spll[0] = hwsq_reg(0x004020);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

525

clk->hwsq.r_spll[1] = hwsq_reg(0x004024);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

526

clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

527

clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

532

clk->hwsq.r_divs = hwsq_reg(0x004800);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

535

clk->hwsq.r_divs = hwsq_reg(0x004700);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c

538

clk->hwsq.r_mast = hwsq_reg(0x00c040);

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h

10

struct hwsq base;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h

20

struct nv50_clk_hwsq hwsq;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

183

nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

185

ram_mask(hwsq, mr[0], 0x100, 0x100);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

186

ram_mask(hwsq, mr[0], 0x100, 0x000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

187

ram_nsec(hwsq, 24000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

191

nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val)

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

193

struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

205

gpio_val = ram_rd32(hwsq, gpio[reg]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

212

ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh));

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

213

ram_nsec(hwsq, 20000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

221

struct nv50_ramseq *hwsq = &ram->hwsq;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

281

ret = ram_init(hwsq, subdev);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

286

ram->base.mr[0] = ram_rd32(hwsq, mr[0]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

287

ram->base.mr[1] = ram_rd32(hwsq, mr[1]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

288

ram->base.mr[2] = ram_rd32(hwsq, mr[2]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

305

ram_mask(hwsq, 0x100710, 0x00000200, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

308

ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

310

ram_wait_vblank(hwsq);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

311

ram_wr32(hwsq, 0x611200, 0x00003300);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

312

ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

313

ram_nsec(hwsq, 8000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

314

ram_setf(hwsq, 0x10, 0x00); /* disable fb */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

315

ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

316

ram_nsec(hwsq, 2000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

319

nv50_ram_gpio(hwsq, 0x2e, 1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

321

ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

322

ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

323

ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

324

ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

325

ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

350

ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

353

ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 |

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

355

ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

356

ram_mask(hwsq, 0x004008, 0x91ff0000, r004008);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

360

ram_wr32(hwsq, 0x100da0, r100da0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

362

nv50_ram_gpio(hwsq, 0x18, !next->bios.ramcfg_FBVDDQ);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

363

ram_nsec(hwsq, 64000); /*XXX*/

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

364

ram_nsec(hwsq, 32000); /*XXX*/

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

366

ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

368

ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

369

ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

370

ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

372

ram_nsec(hwsq, 12000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

376

ram_nuke(hwsq, mr[0]); /* force update */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

377

ram_mask(hwsq, mr[0], 0x000, 0x000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

380

ram_nuke(hwsq, mr[1]); /* force update */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

381

ram_wr32(hwsq, mr[1], ram->base.mr[1]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

382

ram_nuke(hwsq, mr[0]); /* force update */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

383

ram_wr32(hwsq, mr[0], ram->base.mr[0]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

389

ram_mask(hwsq, timing[3], 0xffffffff, timing[3]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

39

struct hwsq base;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

390

ram_mask(hwsq, timing[1], 0xffffffff, timing[1]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

391

ram_mask(hwsq, timing[6], 0xffffffff, timing[6]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

392

ram_mask(hwsq, timing[7], 0xffffffff, timing[7]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

393

ram_mask(hwsq, timing[8], 0xffffffff, timing[8]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

394

ram_mask(hwsq, timing[0], 0xffffffff, timing[0]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

395

ram_mask(hwsq, timing[2], 0xffffffff, timing[2]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

396

ram_mask(hwsq, timing[4], 0xffffffff, timing[4]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

397

ram_mask(hwsq, timing[5], 0xffffffff, timing[5]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

400

ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

401

ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

404

unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000100;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

405

unk714 = ram_rd32(hwsq, 0x100714) & ~0xf0000020;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

406

unk718 = ram_rd32(hwsq, 0x100718) & ~0x00000100;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

407

unk71c = ram_rd32(hwsq, 0x10071c) & ~0x00000100;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

436

ram_mask(hwsq, 0x100714, 0xffffffff, unk714);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

437

ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

438

ram_mask(hwsq, 0x100718, 0xffffffff, unk718);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

439

ram_mask(hwsq, 0x100710, 0xffffffff, unk710);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

444

ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 |

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

447

ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 |

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

449

ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

451

ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

453

ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

456

nv50_ram_gpio(hwsq, 0x2e, 0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

460

nvkm_sddr2_dll_reset(hwsq);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

462

ram_setf(hwsq, 0x10, 0x01); /* enable fb */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

463

ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

464

ram_wr32(hwsq, 0x611200, 0x00003330);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

465

ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

468

ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

470

ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

472

ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

474

ram_mask(hwsq, 0x100710, 0x00000200, 0x00000200);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

484

ram_exec(&ram->hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true));

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

492

ram_exec(&ram->hwsq, false);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

598

ram->hwsq.r_0x002504 = hwsq_reg(0x002504);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

599

ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

600

ram->hwsq.r_0x004008 = hwsq_reg(0x004008);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

601

ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

602

ram->hwsq.r_0x100200 = hwsq_reg(0x100200);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

603

ram->hwsq.r_0x100210 = hwsq_reg(0x100210);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

604

ram->hwsq.r_0x10021c = hwsq_reg(0x10021c);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

605

ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

606

ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

607

ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

608

ram->hwsq.r_0x10053c = hwsq_reg(0x10053c);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

609

ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

610

ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

611

ram->hwsq.r_0x100710 = hwsq_reg(0x100710);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

612

ram->hwsq.r_0x100714 = hwsq_reg(0x100714);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

613

ram->hwsq.r_0x100718 = hwsq_reg(0x100718);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

614

ram->hwsq.r_0x10071c = hwsq_reg(0x10071c);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

615

ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

616

ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

617

ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

618

ram->hwsq.r_0x611200 = hwsq_reg(0x611200);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

621

ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04));

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

624

ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

625

ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

626

ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

627

ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

629

ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

630

ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

631

ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

632

ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

635

ram->hwsq.r_gpio[0] = hwsq_reg(0x00e104);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

636

ram->hwsq.r_gpio[1] = hwsq_reg(0x00e108);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

637

ram->hwsq.r_gpio[2] = hwsq_reg(0x00e120);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

638

ram->hwsq.r_gpio[3] = hwsq_reg(0x00e124);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

68

struct nv50_ramseq hwsq;