CLK_CON_DIV_CLKCMU_TRFM_CORE
CLK_CON_DIV_CLKCMU_TRFM_CORE,
"mout_clkcmu_trfm_core", CLK_CON_DIV_CLKCMU_TRFM_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),