hw_regs
void __iomem *hw_regs = NULL;
hw_regs = ioremap(res.start, resource_size(&res));
if (hw_regs) {
&res.start, hw_regs);
return hw_regs;
u8 *hw_regs;
priv->adapter->hw_regs = NULL;
priv->adapter->hw_regs =
priv->adapter->hw_regs_buf, priv->adapter->hw_regs);
ret = sdio_readsb(card->func, adapter->hw_regs, 0, SDIO_BLOCK_SIZE);
*ireg = adapter->hw_regs[card->reg->host_intstatus];
*val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]);
error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]);
writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]);
writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
writel(count, dev->hw_regs[IRDMA_AEQALLOC]);
readl(dev->hw_regs[IRDMA_CQPERRCODES]));
readl(dev->hw_regs[IRDMA_CQPERRCODES]));
writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]);
statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]);
statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]);
val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);
writel(val, dev->hw_regs[IRDMA_PFHMC_PDINV]);
dev->hw_regs[i] = (u32 __iomem *)(i40iw_regs[i] + hw_addr);
dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
dev->hw_regs[i] = (u32 __iomem *)(hw_addr + icrdma_regs[i]);
dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
pe_criterr = readl(iwdev->rf->sc_dev.hw_regs[IRDMA_GLPE_CRITERR]);
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride));
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride));
u32 __iomem *hw_regs[IRDMA_MAX_REGS];
pfn = ((uintptr_t)ucontext->iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET] +
u64 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
dev->hw_regs[reg_idx] =
dev->hw_regs[reg_idx] = ig3rdma_get_reg_addr(dev->hw,
if (!dev->hw_regs[reg_idx])
dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC];
dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM];
dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC];
dev->cqp_db = dev->hw_regs[IRDMA_CQPDB];
dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK];
struct hw_regs *range = hw_regs_range;
struct hw_regs *range = hw_regs_range;
return be32_to_cpu(descr->hw_regs.dmac_cmd_status) &
be32_to_cpu(descr->hw_regs.dmac_cmd_status) &
descr->hw_regs.next_descr_addr = 0;
descr->prev->hw_regs.next_descr_addr =
be32_to_cpu(card->rx_chain.head->hw_regs.dmac_cmd_status));
be32_to_cpu(card->rx_chain.head->hw_regs.next_descr_addr));
descr->hw_regs.dmac_cmd_status = cpu_to_be32(status |
(be32_to_cpu(descr->hw_regs.dmac_cmd_status) &
descr->hw_regs.next_descr_addr
(descr - 1)->hw_regs.next_descr_addr = 0;
descr->hw_regs.next_descr_addr =
(descr - 1)->hw_regs.next_descr_addr = 0;
descr->hw_regs.dmac_cmd_status = 0;
descr->hw_regs.result_size = 0;
descr->hw_regs.valid_size = 0;
descr->hw_regs.data_error = 0;
descr->hw_regs.payload.dev_addr = 0;
descr->hw_regs.payload.size = 0;
descr->hw_regs.payload.dev_addr = 0; /* tell DMAC don't touch memory */
descr->hw_regs.payload.dev_addr = cpu_to_be32(cpu_addr);
descr->hw_regs.payload.size = cpu_to_be32(GELIC_NET_MAX_FRAME);
descr->hw_regs.payload.dev_addr = cpu_to_be32(cpu_addr);
be32_to_cpu(descr->hw_regs.payload.dev_addr),
descr->hw_regs.payload.dev_addr = 0;
descr->hw_regs.payload.size = 0;
BUG_ON(!(be32_to_cpu(descr->hw_regs.data_status) & GELIC_DESCR_TX_TAIL));
be32_to_cpu(descr->hw_regs.payload.dev_addr), skb->len,
descr->hw_regs.payload.dev_addr = 0;
descr->hw_regs.payload.size = 0;
descr->hw_regs.next_descr_addr = 0;
descr->hw_regs.result_size = 0;
descr->hw_regs.valid_size = 0;
descr->hw_regs.data_status = 0;
descr->hw_regs.data_error = 0;
descr->hw_regs.dmac_cmd_status =
descr->hw_regs.dmac_cmd_status =
descr->hw_regs.dmac_cmd_status =
descr->hw_regs.dmac_cmd_status =
descr->hw_regs.payload.dev_addr = cpu_to_be32(buf);
descr->hw_regs.payload.size = cpu_to_be32(skb->len);
descr->hw_regs.data_status = 0;
descr->hw_regs.next_descr_addr = 0; /* terminate hw descr */
descr->prev->hw_regs.next_descr_addr =
descr->hw_regs.data_status = cpu_to_be32(GELIC_DESCR_TX_TAIL);
descr->prev->hw_regs.next_descr_addr = 0;
data_status = be32_to_cpu(descr->hw_regs.data_status);
data_error = be32_to_cpu(descr->hw_regs.data_error);
be32_to_cpu(descr->hw_regs.payload.dev_addr),
be32_to_cpu(descr->hw_regs.payload.size), DMA_FROM_DEVICE);
skb_put(skb, be32_to_cpu(descr->hw_regs.valid_size)?
be32_to_cpu(descr->hw_regs.valid_size) :
be32_to_cpu(descr->hw_regs.result_size));
if (!descr->hw_regs.valid_size)
be32_to_cpu(descr->hw_regs.result_size),
be32_to_cpu(descr->hw_regs.payload.size),
be32_to_cpu(descr->hw_regs.dmac_cmd_status));
struct gelic_hw_regs hw_regs;
const struct ath12k_hw_regs *hw_regs;
.hw_regs = &qcn9274_v1_regs,
.hw_regs = &qcn9274_v2_regs,
.hw_regs = &wcn7850_regs,
.hw_regs = &ipq5332_regs,
.hw_regs = &qcc2072_regs,
.hw_regs = &ipq5424_regs,
hal->regs = ath12k_wifi7_hw_ver_map[ab->hw_rev].hw_regs;