hw_context
u32 *preg = rctx->state.hw_context;
u32 *preg = state->hw_context;
u32 hw_context[3 + HASH_CSR_NB_MAX];
memcpy(areq->result, req_ctx->hw_context,
req_ctx->hw_context,
req_ctx->hw_context, DMA_FROM_DEVICE);
req_ctx->hw_context,
dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
req_ctx->hw_context[0] = SHA224_H0;
req_ctx->hw_context[1] = SHA224_H1;
req_ctx->hw_context[2] = SHA224_H2;
req_ctx->hw_context[3] = SHA224_H3;
req_ctx->hw_context[4] = SHA224_H4;
req_ctx->hw_context[5] = SHA224_H5;
req_ctx->hw_context[6] = SHA224_H6;
req_ctx->hw_context[7] = SHA224_H7;
req_ctx->hw_context[8] = 0;
req_ctx->hw_context[9] = 0;
dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
memcpy(export->hw_context, req_ctx->hw_context,
memcpy(req_ctx->hw_context, export->hw_context, size);
dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
pd->hw_context = hw_context;
pd->hw_context = -1;
if (pd->hw_context != -1) {
PSB_WSGX32(0, PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
if (pd->driver->has_clflush && pd->hw_context != -1) {
if (pd->hw_context != -1) {
if (pd->hw_context != -1) {
if (pd->hw_context != -1)
if (pd->hw_context != -1)
if (pd->hw_context != -1)
if (pd->hw_context != -1)
if (pd->hw_context != -1)
if (pd->hw_context != -1)
if (pd->hw_context != -1)
if (pd->hw_context != -1)
int hw_context;
extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
reg = read_kctxt_csr(dd, sc->hw_context,
write_kctxt_csr(dd, sc->hw_context,
hw_ctxt = rcd->sc->hw_context;
hw_ctxt = rcd->sc->hw_context;
hw_ctxt = rcd->sc->hw_context;
hw_ctxt = ctxt->sc->hw_context;
unsigned int hw_context)
sw_index = dd->hw_to_sw[hw_context];
sw_index, hw_context);
sw_index, hw_context);
status = read_kctxt_csr(dd, hw_context, SEND_CTXT_ERR_STATUS);
dd_dev_info(dd, "Send Context %u(%u) Error: %s\n", sw_index, hw_context,
cinfo.send_ctxt = uctxt->sc->hw_context;
(uctxt->sc->hw_context * BIT(16))) +
uctxt->sc->hw_context);
sc->hw_context);
reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS));
__func__, sc->sw_index, sc->hw_context);
sc->hw_context, count);
sc_ctrl = read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS));
write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg);
pio = ((sc->hw_context & SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK) <<
sc->sw_index, sc->hw_context, ret);
write_kctxt_csr(dd, sc->hw_context, SC(CTRL), sc_ctrl);
read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE),
read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE));
write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), 0);
write_kctxt_csr(sc->dd, sc->hw_context,
write_kctxt_csr(sc->dd, sc->hw_context,
void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
sw_index = dd->hw_to_sw[hw_context];
__func__, hw_context, sw_index);
gc = group_context(hw_context, sc->group);
__func__, hw_context, sw_index);
ctxt = dd->vld[15].sc->hw_context;
ctxt = dd->vld[i].sc->hw_context;
ctxt = dd->kernel_send_context[i + 1]->hw_context;
sc->flags, sc->sw_index, sc->hw_context, sc->group);
reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_STATUS));
u32 *hw_context)
*hw_context = context;
static void sc_hw_free(struct hfi1_devdata *dd, u32 sw_index, u32 hw_context)
__func__, sw_index, hw_context);
dd->hw_to_sw[hw_context] = INVALID_SCI;
u32 gc = group_context(sc->hw_context, sc->group);
u32 index = sc->hw_context & 0x7;
write_kctxt_csr(sc->dd, sc->hw_context,
u32 hw_context = sc->hw_context;
write_kctxt_csr(dd, hw_context,
u32 hw_context;
ret = sc_hw_alloc(dd, type, &sw_index, &hw_context);
sc->hw_context = hw_context;
sc->base_addr = dd->piobase + ((hw_context & PIO_ADDR_CONTEXT_MASK)
write_kctxt_csr(dd, hw_context, SC(CTRL), reg);
write_kctxt_csr(dd, hw_context, SC(ERR_MASK), (u64)-1);
write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY),
write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE),
write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), reg);
write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), reg);
write_kctxt_csr(dd, hw_context, SC(CHECK_VL), reg);
hw_context,
u32 hw_context;
hw_context = sc->hw_context;
write_kctxt_csr(dd, hw_context, SC(CTRL), 0);
write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), 0);
write_kctxt_csr(dd, hw_context, SC(ERR_MASK), 0);
write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY), 0);
write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE), 0);
write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), 0);
write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), 0);
sc_hw_free(dd, sw_index, hw_context);
reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL));
write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg);
static bool is_sc_halted(struct hfi1_devdata *dd, u32 hw_context)
return !!(read_kctxt_csr(dd, hw_context, SC(STATUS)) &
reg = read_csr(dd, sc->hw_context * 8 +
is_sc_halted(dd, sc->hw_context) || egress_halted(reg))
sc->hw_context, (u32)reg);
void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
u8 hw_context; /* hardware context number */
__field(u32, hw_context)
__entry->hw_context = sc->hw_context;
__entry->hw_context,
__field(u32, hw_context)
__entry->hw_context = sc->hw_context;
__entry->hw_context,
struct hw_context context[ILT_MAX_L2_LINES];