CLK_CFG_7
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISPPWM_SEL, "disppwm_sel", disppwm_sel_parents, CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 0, 2, 7, 0, 0),
ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR,