CLK_CFG_4_CLR
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 0, 2, 7, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 8, 2, 15, 0, 0),
MUX_CLR_SET_UPD(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 16, 3, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_sel_parents, CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, 24, 2, 31, 0, 0),
CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16),
CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR,
CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18),
CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19),
CLK_CFG_4_CLR, 0, 2,
CLK_CFG_4_CLR, 8, 2,