CLK_CFG_3
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 0, 4, 7, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 8, 3, 15, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_2_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 16, 3, 23, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_sel_parents, CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, 24, 4, 31, 0, 0),
msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
ap2conn_host_parents, CLK_CFG_3, CLK_CFG_3_SET,
atb_parents, CLK_CFG_3, CLK_CFG_3_SET,