drivers/clk/mediatek/clk-mt6735-topckgen.c

339

MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, 0, 0),

drivers/clk/mediatek/clk-mt6735-topckgen.c

340

MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 3, 15, 0, 0),

drivers/clk/mediatek/clk-mt6735-topckgen.c

341

MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 4, 23, 0, 0),

drivers/clk/mediatek/clk-mt6735-topckgen.c

342

MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, 0, 0),

drivers/clk/mediatek/clk-mt6765.c

384

CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,

drivers/clk/mediatek/clk-mt6765.c

387

CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,

drivers/clk/mediatek/clk-mt6765.c

390

camtg_parents, CLK_CFG_1, CLK_CFG_1_SET,

drivers/clk/mediatek/clk-mt6765.c

393

CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,

drivers/clk/mediatek/clk-mt8196-topckgen.c

635

shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,

drivers/clk/mediatek/clk-mt8196-topckgen.c

639

shared_axi_parents, CLK_CFG_1, CLK_CFG_1_SET,

drivers/clk/mediatek/clk-mt8196-topckgen.c

643

shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,

drivers/clk/mediatek/clk-mt8196-topckgen.c

647

shared_sub_parents, CLK_CFG_1, CLK_CFG_1_SET,