CLK_CFG_1_CLR
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 3, 15, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 16, 4, 23, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_sel_parents, CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, 24, 3, 31, 0, 0),
CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,
CLK_CFG_1_CLR, 0, 3,
CLK_CFG_1_CLR, 8, 3,
CLK_CFG_1_CLR, 16, 4,
CLK_CFG_1_CLR, 24, 4,