CLK_CFG_0_SET
MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, 0, 0),
MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 1, 0, 0),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, 0, 0),
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
axi_parents, CLK_CFG_0, CLK_CFG_0_SET,
mem_sub_parents, CLK_CFG_0, CLK_CFG_0_SET,
io_noc_parents, CLK_CFG_0, CLK_CFG_0_SET,
shared_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,