drivers/clk/mediatek/clk-mt6735-topckgen.c

335

MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 0, 3, 0, 0),

drivers/clk/mediatek/clk-mt6735-topckgen.c

336

MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),

drivers/clk/mediatek/clk-mt6735-topckgen.c

337

MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 1, 0, 0),

drivers/clk/mediatek/clk-mt6735-topckgen.c

338

MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, 0, 0),

drivers/clk/mediatek/clk-mt6765.c

369

CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,

drivers/clk/mediatek/clk-mt6765.c

373

CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,

drivers/clk/mediatek/clk-mt6765.c

377

CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,

drivers/clk/mediatek/clk-mt6765.c

380

CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,

drivers/clk/mediatek/clk-mt8196-topckgen.c

618

axi_parents, CLK_CFG_0, CLK_CFG_0_SET,

drivers/clk/mediatek/clk-mt8196-topckgen.c

622

mem_sub_parents, CLK_CFG_0, CLK_CFG_0_SET,

drivers/clk/mediatek/clk-mt8196-topckgen.c

626

io_noc_parents, CLK_CFG_0, CLK_CFG_0_SET,

drivers/clk/mediatek/clk-mt8196-topckgen.c

630

shared_axi_parents, CLK_CFG_0, CLK_CFG_0_SET,