ia_css_device_store_uint32
ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
ia_css_device_store_uint32(reg_loc, value);
ia_css_device_store_uint32(reg_addr, value);
ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] +
ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data),
ia_css_device_store_uint32(DMA_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(event_sink_addr[ID], token);
ia_css_device_store_uint32(FIFO_MONITOR_BASE[ID] + reg * sizeof(hrt_data),
ia_css_device_store_uint32(GDC_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value);
ia_css_device_store_uint32((GP_TIMER_BASE +
ia_css_device_store_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr, value);
ia_css_device_store_uint32(IRQ_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(ISP_DMEM_BASE[ID] + addr, data);
ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(SP_DMEM_BASE[SP0_ID] + addr, data);
ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(TIMED_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
void ia_css_device_store_uint32(
ia_css_device_store_uint32(MMU_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(const hrt_address addr, const uint32_t data);
ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof(hrt_data),
ia_css_device_store_uint32(RX_BASE[ID] + reg * sizeof(hrt_data), value);
ia_css_device_store_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg *
ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] +
ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);