hr_reg_read
if (hr_reg_read(resp, FUNC_CLEAR_RST_FUN_DONE)) {
caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num;
caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num;
caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num;
caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num;
caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num;
caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num;
caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num;
caps->sccc_bt_num = hr_reg_read(r_b, FUNC_RES_B_SCCC_BT_NUM) / func_num;
caps->sl_num = hr_reg_read(r_b, FUNC_RES_V_QID_NUM) / func_num;
caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_V_GMV_BT_NUM) /
caps->sl_num = hr_reg_read(r_b, FUNC_RES_B_QID_NUM) / func_num;
caps->gmv_bt_num = hr_reg_read(r_b, FUNC_RES_B_GMV_BT_NUM) /
caps->qpc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_QPC_ITEM_NUM);
caps->cqc_timer_bt_num = hr_reg_read(req, PF_TIMER_RES_CQC_ITEM_NUM);
caps->num_pds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_PDS);
caps->flags = hr_reg_read(resp_c, PF_CAPS_C_CAP_FLAGS);
caps->num_cqs = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_CQS);
caps->gid_table_len[0] = hr_reg_read(resp_c, PF_CAPS_C_MAX_GID);
caps->max_cqes = 1 << hr_reg_read(resp_c, PF_CAPS_C_CQ_DEPTH);
caps->num_xrcds = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_XRCDS);
caps->num_mtpts = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_MRWS);
caps->num_qps = 1 << hr_reg_read(resp_c, PF_CAPS_C_NUM_QPS);
caps->max_qp_init_rdma = hr_reg_read(resp_c, PF_CAPS_C_MAX_ORD);
caps->num_srqs = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_SRQS);
caps->cong_cap = hr_reg_read(resp_d, PF_CAPS_D_CONG_CAP);
caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);
caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);
caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);
caps->default_cong_type = hr_reg_read(resp_d, PF_CAPS_D_DEFAULT_ALG);
caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);
caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);
caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
caps->reserved_uars = hr_reg_read(resp_d, PF_CAPS_D_RSV_UARS);
caps->reserved_mrws = hr_reg_read(resp_e, PF_CAPS_E_RSV_MRWS);
caps->chunk_sz = 1 << hr_reg_read(resp_e, PF_CAPS_E_CHUNK_SIZE_SHIFT);
caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);
caps->reserved_xrcds = hr_reg_read(resp_e, PF_CAPS_E_RSV_XRCDS);
caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);
caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);
caps->wqe_sq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_SQWQE_HOP_NUM);
caps->wqe_sge_hop_num = hr_reg_read(resp_d, PF_CAPS_D_EX_SGE_HOP_NUM);
caps->wqe_rq_hop_num = hr_reg_read(resp_d, PF_CAPS_D_RQWQE_HOP_NUM);
hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);
hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);
return (hr_reg_read(cqe, CQE_OWNER) ^ !!(n & hr_cq->cq_depth)) ? cqe :
if (hr_reg_read(cqe, CQE_LCL_QPN) == qpn) {
if (srq && hr_reg_read(cqe, CQE_S_R)) {
wqe_index = hr_reg_read(cqe, CQE_WQE_IDX);
owner_bit = hr_reg_read(dest, CQE_OWNER);
u32 cqe_status = hr_reg_read(cqe, CQE_STATUS);
wc->vendor_err = hr_reg_read(cqe, CQE_SUB_STATUS);
qpn = hr_reg_read(cqe, CQE_LCL_QPN);
hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
hr_opcode = hr_reg_read(cqe, CQE_OPCODE);
wc->sl = hr_reg_read(cqe, CQE_SL);
wc->src_qp = hr_reg_read(cqe, CQE_RMT_QPN);
wc->wc_flags |= hr_reg_read(cqe, CQE_GRH) ? IB_WC_GRH : 0;
wc->port_num = hr_reg_read(cqe, CQE_PORTN);
if (hr_reg_read(cqe, CQE_VID_VLD)) {
wc->vlan_id = hr_reg_read(cqe, CQE_VID);
wc->network_hdr_type = hr_reg_read(cqe, CQE_PORT_TYPE);
wqe_idx = hr_reg_read(cqe, CQE_WQE_IDX);
is_send = !hr_reg_read(cqe, CQE_S_R);
timeout = (u8)hr_reg_read(context, QPC_AT);
state = hr_reg_read(&context, QPC_QP_ST);
qp_attr->path_mtu = (enum ib_mtu)hr_reg_read(&context, QPC_MTU);
qp_attr->rq_psn = hr_reg_read(&context, QPC_RX_REQ_EPSN);
qp_attr->sq_psn = (u32)hr_reg_read(&context, QPC_SQ_CUR_PSN);
qp_attr->dest_qp_num = hr_reg_read(&context, QPC_DQPN);
((hr_reg_read(&context, QPC_RRE)) << V2_QP_RRE_S) |
((hr_reg_read(&context, QPC_RWE)) << V2_QP_RWE_S) |
((hr_reg_read(&context, QPC_ATE)) << V2_QP_ATE_S);
hr_reg_read(&context, QPC_SL));
grh->flow_label = hr_reg_read(&context, QPC_FL);
grh->sgid_index = hr_reg_read(&context, QPC_GMV_IDX);
grh->hop_limit = hr_reg_read(&context, QPC_HOPLIMIT);
grh->traffic_class = hr_reg_read(&context, QPC_TC);
qp_attr->max_rd_atomic = 1 << hr_reg_read(&context, QPC_SR_MAX);
qp_attr->max_dest_rd_atomic = 1 << hr_reg_read(&context, QPC_RR_MAX);
qp_attr->min_rnr_timer = (u8)hr_reg_read(&context, QPC_MIN_RNR_TIME);
qp_attr->retry_cnt = hr_reg_read(&context, QPC_RETRY_NUM_INIT);
qp_attr->rnr_retry = hr_reg_read(&context, QPC_RNR_NUM_INIT);
attr->srq_limit = hr_reg_read(srq_context, SRQC_LIMIT_WL);
return (hr_reg_read(aeqe, AEQE_OWNER) ^
event_type = hr_reg_read(aeqe, AEQE_EVENT_TYPE);
sub_type = hr_reg_read(aeqe, AEQE_SUB_TYPE);
queue_num = hr_reg_read(aeqe, AEQE_EVENT_QUEUE_NUM);
return (hr_reg_read(ceqe, CEQE_OWNER) ^
ecc_info->is_ecc_err = hr_reg_read(req, QUERY_RAM_ECC_1BIT_ERR);
ecc_info->res_type = hr_reg_read(req, QUERY_RAM_ECC_RES_TYPE);
ecc_info->index = hr_reg_read(req, QUERY_RAM_ECC_TAG);
addr_low = hr_reg_read(req, CFG_GMV_BT_BA_L);
addr_upper = hr_reg_read(req, CFG_GMV_BT_BA_H);
cqn = hr_reg_read(ceqe, CEQE_CQN);