drivers/gpu/drm/i915/display/i9xx_plane.c

700

i915_enable_pipestat(display, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);

drivers/gpu/drm/i915/display/intel_display_irq.c

1653

i915_enable_pipestat(display, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1695

i915_enable_pipestat(display, pipe,

drivers/gpu/drm/i915/display/intel_display_irq.c

1991

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

1992

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2005

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2006

i915_enable_pipestat(display, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2007

i915_enable_pipestat(display, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2038

i915_enable_pipestat(display, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

2040

i915_enable_pipestat(display, pipe, pipestat_mask);

drivers/gpu/drm/i915/display/intel_display_irq.c

411

i915_enable_pipestat(display, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);

drivers/gpu/drm/i915/display/intel_display_irq.c

413

i915_enable_pipestat(display, PIPE_A,

drivers/gpu/drm/i915/display/intel_display_irq.h

77

void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask);

drivers/gpu/drm/i915/display/intel_tv.c

1670

i915_enable_pipestat(display, 0,