hpet_base
hpet_base.channels = hc;
hpet_base.nr_channels = channels;
hpet_base.boot_cfg = cfg;
hpet_legacy_clockevent_register(&hpet_base.channels[0]);
hpet_base.channels[0].mode = HPET_MODE_LEGACY;
hpet_base.channels[1].mode = HPET_MODE_LEGACY;
kfree(hpet_base.channels);
hpet_base.channels = NULL;
hpet_base.nr_channels = 0;
if (!hpet_base.nr_clockevents)
cfg = hpet_base.boot_cfg;
for (i = 0; i < hpet_base.nr_channels; i++)
hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i));
if (hpet_base.boot_cfg & HPET_CFG_ENABLE)
hpet_writel(hpet_base.boot_cfg, HPET_CFG);
struct clock_event_device *evt = &hpet_base.channels[0].evt;
struct clock_event_device *evt = &hpet_base.channels[0].evt;
hd.hd_nirqs = hpet_base.nr_channels;
for (i = 0; i < hpet_base.nr_channels; i++) {
struct hpet_channel *hc = hpet_base.channels + i;
for (i = 0; i < hpet_base.nr_channels; i++) {
struct hpet_channel *hc = hpet_base.channels + i;
static struct hpet_base hpet_base;
for (i = 0; i < hpet_base.nr_channels; i++) {
struct hpet_channel *hc = hpet_base.channels + i;
hpet_base.nr_clockevents = 0;
for (i = 0; i < hpet_base.nr_channels; i++) {
struct hpet_channel *hc = hpet_base.channels + i;
if (++hpet_base.nr_clockevents == num_possible_cpus())
hpet_base.nr_channels, hpet_base.nr_clockevents);