i8
uint64_t i8;
result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
struct m16e_i8 i8;
if (mips16inst.i8.func != MIPS16e_swrasp_func)
u8 i8 = index & 0xff;
if (drm_WARN_ON_ONCE(dev, index != i8))
ast_io_write8(ast, AST_IO_VGADWR, i8);
u8 i8 = index & 0xff;
if (drm_WARN_ON_ONCE(dev, index != i8))
WREG8(DAC_INDEX + MGA1064_INDEX, i8);
u8 i8 = index & 0xff;
if (drm_WARN_ON_ONCE(dev, index != i8))
odev->funcs->cmap_write(odev, i8, r8, g8, b8);
u8 i8 = index & 0xff;
if (drm_WARN_ON_ONCE(dev, index != i8))
vesa->cmap_write(vesa, i8, red, green, blue);
u8 i8 = index;
outb_p(i8, VGA_PEL_IW);
#define PhysicalMinimum_i8(min_) 0x35, i8(min_),
#define PhysicalMaximum_i8(max_) 0x45, i8(max_),
#define UsageMinimum_i8(min_) 0x19, i8(min_),
#define UsageMaximum_i8(max_) 0x29, i8(max_),
#define UsagePage_i8(p_) 0x05, i8(p_),
#define Usage_i8(u_) 0x09, i8(u_),
#define Unit_i8(u_) 0x65, i8(u_),
#define Collection(col_, ...) 0xa1, i8(col_), __VA_ARGS__ 0xc0,
#define Input(i_) 0x081, i8(i_),
#define Output(i_) 0x091, i8(i_),
#define Feature(i_) 0x0b1, i8(i_),
#define ReportId(id_) 0x85, i8(id_),
#define ReportSize(sz_) 0x75, i8(sz_),
#define ReportCount(cnt_) 0x95, i8(cnt_),
#define LogicalMinimum_i8(min_) 0x15, i8(min_),
#define LogicalMaximum_i8(max_) 0x25, i8(max_),
u16 areg, enum shf_op op, u16 breg, bool i8, bool sw, bool wr_both,
FIELD_PREP(OP_SHF_I8, i8) |
reg.areg, op, reg.breg, reg.i8, reg.swap, reg.wr_both,
reg.i8, zero, reg.swap, reg.wr_both,
static u16 nfp_swreg_to_rereg(swreg reg, bool is_dst, bool has_imm8, bool *i8)
*i8 = val & 0x80;
reg->areg = nfp_swreg_to_rereg(rreg, false, has_imm8, ®->i8);
reg->breg = nfp_swreg_to_rereg(lreg, false, has_imm8, ®->i8);
reg->areg = nfp_swreg_to_rereg(lreg, false, has_imm8, ®->i8);
reg->breg = nfp_swreg_to_rereg(rreg, false, has_imm8, ®->i8);
bool i8;
u32 i8;