i40e_write_rx_ctl
i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, flow_id),
i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, flow_id),
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
i40e_write_rx_ctl(&pf->hw,
i40e_write_rx_ctl(&pf->hw,
i40e_write_rx_ctl(&pf->hw,
i40e_write_rx_ctl(&pf->hw,
i40e_write_rx_ctl(&pf->hw,
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(0, vf->vf_id),
i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(1, vf->vf_id),
i40e_write_rx_ctl(hw,
i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),