i40e_read_rx_ctl
val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
i_set = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
i_setc = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, flow_id)) |
((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, flow_id)) << 32);
seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);