drivers/gpu/host1x/dev.h

186

u32 host1x_ch_readl(struct host1x_channel *ch, u32 r);

drivers/gpu/host1x/hw/cdma_hw.c

125

host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET),

drivers/gpu/host1x/hw/cdma_hw.c

126

host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT),

drivers/gpu/host1x/hw/cdma_hw.c

213

__func__, host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET),

drivers/gpu/host1x/hw/cdma_hw.c

214

host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT),

drivers/gpu/host1x/hw/debug_hw_1x01.c

24

dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART);

drivers/gpu/host1x/hw/debug_hw_1x01.c

25

dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND);

drivers/gpu/host1x/hw/debug_hw_1x01.c

26

dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);

drivers/gpu/host1x/hw/debug_hw_1x01.c

27

dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);

drivers/gpu/host1x/hw/debug_hw_1x01.c

28

dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);

drivers/gpu/host1x/hw/debug_hw_1x01.c

80

val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);

drivers/gpu/host1x/hw/debug_hw_1x06.c

25

dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART_HI);

drivers/gpu/host1x/hw/debug_hw_1x06.c

28

dmastart |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART);

drivers/gpu/host1x/hw/debug_hw_1x06.c

31

dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND_HI);

drivers/gpu/host1x/hw/debug_hw_1x06.c

34

dmaend |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND);

drivers/gpu/host1x/hw/debug_hw_1x06.c

36

dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);

drivers/gpu/host1x/hw/debug_hw_1x06.c

37

dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);

drivers/gpu/host1x/hw/debug_hw_1x06.c

38

dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);

drivers/gpu/host1x/hw/debug_hw_1x06.c

39

offset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET);

drivers/gpu/host1x/hw/debug_hw_1x06.c

40

class = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);

drivers/gpu/host1x/hw/debug_hw_1x06.c

41

ch_stat = host1x_ch_readl(ch, HOST1X_CHANNEL_CHANNELSTAT);

drivers/gpu/host1x/hw/debug_hw_1x06.c

79

val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);

drivers/gpu/host1x/hw/debug_hw_1x06.c

86

val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);