i2s_write_reg
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1);
i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1);
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
i2s_write_reg(dev->i2s_base, IER, reg);
i2s_write_reg(dev->i2s_base, ITER, 1);
i2s_write_reg(dev->i2s_base, IRER, 1);
i2s_write_reg(dev->i2s_base, CER, 1);
i2s_write_reg(dev->i2s_base, ITER, 0);
i2s_write_reg(dev->i2s_base, IRER, 0);
i2s_write_reg(dev->i2s_base, CER, 0);
i2s_write_reg(dev->i2s_base, IER, 0);
i2s_write_reg(dev->i2s_base, TCR(ch_reg),
i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |
i2s_write_reg(dev->i2s_base, RCR(ch_reg),
i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |
i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
i2s_write_reg(dev->i2s_base, TXFFR, 1);
i2s_write_reg(dev->i2s_base, RXFFR, 1);
i2s_write_reg(dev->i2s_base, TER(i), 0);
i2s_write_reg(dev->i2s_base, RER(i), 0);
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);