i2c_op
i2c_op(pd, OP_TX_STOP);
i2c_op(pd, OP_TX_FIRST);
i2c_op(pd, OP_TX);
i2c_op(pd, OP_TX_FIRST);
i2c_op(pd, OP_TX_TO_RX);
i2c_op(pd, OP_RX_STOP);
i2c_op(pd, OP_RX_STOP);
pd->msg->buf[real_pos] = i2c_op(pd, OP_RX_STOP_DATA);
pd->msg->buf[real_pos] = i2c_op(pd, OP_RX);
i2c_op(pd, OP_START);
if (0 != dev->i2c_op) {
dev->i2c_op = 0;
*dword, saa7146_read(dev, I2C_STATUS), dev->i2c_op);
dev->i2c_op = 1;
timeout = wait_event_interruptible_timeout(dev->i2c_wq, dev->i2c_op == 0, timeout);
if (timeout == -ERESTARTSYS || dev->i2c_op) {
struct xgbe_i2c_op *i2c_op)
return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
struct xgbe_i2c_op i2c_op;
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = phy_data->redrv_addr;
i2c_op.len = sizeof(redrv_data);
i2c_op.buf = redrv_data;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
i2c_op.cmd = XGBE_I2C_CMD_READ;
i2c_op.target = phy_data->redrv_addr;
i2c_op.len = 1;
i2c_op.buf = redrv_data;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
struct xgbe_i2c_op i2c_op;
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = target;
i2c_op.len = val_len;
i2c_op.buf = val;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
struct xgbe_i2c_op i2c_op;
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = target;
i2c_op.len = reg_len;
i2c_op.buf = reg;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
i2c_op.cmd = XGBE_I2C_CMD_READ;
i2c_op.target = target;
i2c_op.len = val_len;
i2c_op.buf = val;
ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
struct xgbe_i2c_op i2c_op;
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = phy_data->sfp_mux_address;
i2c_op.len = sizeof(mux_channel);
i2c_op.buf = &mux_channel;
return xgbe_phy_i2c_xfer(pdata, &i2c_op);
struct xgbe_i2c_op i2c_op;
i2c_op.cmd = XGBE_I2C_CMD_WRITE;
i2c_op.target = phy_data->sfp_mux_address;
i2c_op.len = sizeof(mux_channel);
i2c_op.buf = &mux_channel;
return xgbe_phy_i2c_xfer(pdata, &i2c_op);
enum i2c_op op;
int i2c_op;