Symbol: CLK_BASE
drivers/clk/ralink/clk-mt7621.c
310
{ CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) },
drivers/clk/ralink/clk-mt7621.c
311
{ CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) },
drivers/clk/ralink/clk-mt7621.c
312
{ CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
702
{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
703
{ CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
drivers/clk/ralink/clk-mtmips.c
707
{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
708
{ CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
drivers/clk/ralink/clk-mtmips.c
712
{ CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
713
{ CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
drivers/clk/ralink/clk-mtmips.c
717
{ CLK_BASE("xtal", NULL, rt2880_xtal_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
718
{ CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
719
{ CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
drivers/clk/ralink/clk-mtmips.c
723
{ CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
724
{ CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
725
{ CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
drivers/clk/ralink/clk-mtmips.c
729
{ CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
730
{ CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
731
{ CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
732
{ CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
733
{ CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
drivers/clk/ralink/clk-mtmips.c
737
{ CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
drivers/clk/ralink/clk-mtmips.c
738
{ CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c
53
adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
53
adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
51
adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
51
(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
59
(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
71
(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
105
(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
69
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } },
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
85
.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
187
.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
191
.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
198
.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
215
.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
drivers/gpu/drm/amd/include/aldebaran_ip_offset.h
42
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
drivers/gpu/drm/amd/include/arct_ip_offset.h
45
static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },
drivers/gpu/drm/amd/include/beige_goby_ip_offset.h
45
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
drivers/gpu/drm/amd/include/cyan_skillfish_ip_offset.h
43
static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } },
drivers/gpu/drm/amd/include/dimgrey_cavefish_ip_offset.h
44
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
drivers/gpu/drm/amd/include/navi10_ip_offset.h
43
static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } },
drivers/gpu/drm/amd/include/navi12_ip_offset.h
44
static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
drivers/gpu/drm/amd/include/navi14_ip_offset.h
44
static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
drivers/gpu/drm/amd/include/renoir_ip_offset.h
51
static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h
44
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
drivers/gpu/drm/amd/include/vangogh_ip_offset.h
56
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
drivers/gpu/drm/amd/include/vega10_ip_offset.h
201
static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
drivers/gpu/drm/amd/include/vega20_ip_offset.h
43
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } },
drivers/gpu/drm/amd/include/yellow_carp_offset.h
33
static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },