arch/x86/events/core.c

401

val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];

arch/x86/events/core.c

409

attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];

arch/x86/events/intel/core.c

3975

return &hybrid_var(cpuc->pmu, unconstrained);

arch/x86/events/intel/core.c

7452

memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));

arch/x86/events/intel/core.c

7453

memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));

arch/x86/events/intel/core.c

7471

memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));

arch/x86/events/intel/core.c

7472

memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));

arch/x86/events/intel/core.c

7473

hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;

arch/x86/events/intel/core.c

7494

memcpy(hybrid_var(pmu, hw_cache_event_ids),

arch/x86/events/intel/core.c

7496

memcpy(hybrid_var(pmu, hw_cache_extra_regs),

arch/x86/events/intel/core.c

7516

memcpy(hybrid_var(pmu, hw_cache_extra_regs),

arch/x86/events/intel/ds.c

464

val = hybrid_var(event->pmu, pebs_data_source)[dse];

arch/x86/events/intel/ds.c

546

val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK];

arch/x86/events/intel/ds.c

650

val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];

arch/x86/events/intel/ds.c

700

val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];