drivers/gpu/drm/i915/gt/gen2_engine_cs.c

148

GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

378

GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

398

GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

433

return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1322

frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2024

hwsp_seqno(rq),

drivers/gpu/drm/i915/gt/intel_engine_pm.c

85

READ_ONCE(*ce->timeline->hwsp_seqno),

drivers/gpu/drm/i915/gt/intel_engine_pm.c

88

READ_ONCE(*ce->timeline->hwsp_seqno));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

1984

hwsp_seqno(rq));

drivers/gpu/drm/i915/gt/intel_timeline.c

226

u32 *hwsp_seqno = (u32 *)tl->hwsp_seqno;

drivers/gpu/drm/i915/gt/intel_timeline.c

230

memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno));

drivers/gpu/drm/i915/gt/intel_timeline.c

231

WRITE_ONCE(*hwsp_seqno, tl->seqno);

drivers/gpu/drm/i915/gt/intel_timeline.c

232

drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES);

drivers/gpu/drm/i915/gt/intel_timeline.c

319

tl->hwsp_seqno = tl->hwsp_map + next_ofs;

drivers/gpu/drm/i915/gt/intel_timeline.c

323

GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno));

drivers/gpu/drm/i915/gt/intel_timeline.c

356

offset_in_page(from->hwsp_seqno);

drivers/gpu/drm/i915/gt/intel_timeline.c

457

*tl->hwsp_seqno, tl->seqno);

drivers/gpu/drm/i915/gt/intel_timeline.c

70

timeline->hwsp_seqno = memset(vaddr + ofs, 0, TIMELINE_SEQNO_BYTES);

drivers/gpu/drm/i915/gt/intel_timeline.c

98

timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset;

drivers/gpu/drm/i915/gt/intel_timeline_types.h

47

const u32 *hwsp_seqno;

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

203

cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

359

(rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

360

(rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);

drivers/gpu/drm/i915/gt/selftest_rc6.c

183

result = rq->hwsp_seqno + 2;

drivers/gpu/drm/i915/gt/selftest_timeline.c

1201

WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

1288

WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

1389

if (READ_ONCE(*tl->hwsp_seqno) != count) {

drivers/gpu/drm/i915/gt/selftest_timeline.c

1392

tl->hwsp_offset, *tl->hwsp_seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

496

if (READ_ONCE(*tl->hwsp_seqno) != tl->seqno) {

drivers/gpu/drm/i915/gt/selftest_timeline.c

498

*tl->hwsp_seqno, tl->seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

582

if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {

drivers/gpu/drm/i915/gt/selftest_timeline.c

584

n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

652

if (!err && READ_ONCE(*tl->hwsp_seqno) != n) {

drivers/gpu/drm/i915/gt/selftest_timeline.c

654

n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

691

const u32 *hwsp_seqno[2];

drivers/gpu/drm/i915/gt/selftest_timeline.c

721

hwsp_seqno[0] = tl->hwsp_seqno;

drivers/gpu/drm/i915/gt/selftest_timeline.c

738

hwsp_seqno[1] = tl->hwsp_seqno;

drivers/gpu/drm/i915/gt/selftest_timeline.c

742

GEM_BUG_ON(hwsp_seqno[0] == hwsp_seqno[1]);

drivers/gpu/drm/i915/gt/selftest_timeline.c

752

if (READ_ONCE(*hwsp_seqno[0]) != seqno[0] ||

drivers/gpu/drm/i915/gt/selftest_timeline.c

753

READ_ONCE(*hwsp_seqno[1]) != seqno[1]) {

drivers/gpu/drm/i915/gt/selftest_timeline.c

755

*hwsp_seqno[0], *hwsp_seqno[1],

drivers/gpu/drm/i915/i915_gpu_error.c

1476

e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ?

drivers/gpu/drm/i915/i915_gpu_error.c

1477

*ce->timeline->hwsp_seqno : ~0U;

drivers/gpu/drm/i915/i915_gpu_error.c

509

err_printf(m, " context timeline seqno %u\n", ctx->hwsp_seqno);

drivers/gpu/drm/i915/i915_gpu_error.h

111

u32 hwsp_seqno;

drivers/gpu/drm/i915/i915_request.c

961

rq->hwsp_seqno = tl->hwsp_seqno;

drivers/gpu/drm/i915/i915_request.h

279

const u32 *hwsp_seqno;

drivers/gpu/drm/i915/i915_request.h

487

const u32 *hwsp = READ_ONCE(rq->hwsp_seqno);

drivers/gpu/drm/i915/i915_request.h

630

WRITE_ONCE(rq->hwsp_seqno, /* decouple from HWSP */

drivers/gpu/drm/i915/i915_request.h

69

hwsp_seqno(rq__), ##__VA_ARGS__); \

drivers/gpu/drm/i915/i915_request.h

698

u32 hwsp_relative_offset = offset_in_page(rq->hwsp_seqno);