drivers/gpu/drm/i915/gt/gen8_engine_cs.c

433

return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno);

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

449

*cs++ = hwsp_offset(rq);

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

661

return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

682

hwsp_offset(rq),

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

703

hwsp_offset(rq),

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

849

hwsp_offset(rq),

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2023

tl ? tl->hwsp_offset : 0,

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2304

tl->hwsp_offset);

drivers/gpu/drm/i915/gt/intel_timeline.c

100

GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);

drivers/gpu/drm/i915/gt/intel_timeline.c

209

tl->hwsp_offset =

drivers/gpu/drm/i915/gt/intel_timeline.c

211

offset_in_page(tl->hwsp_offset);

drivers/gpu/drm/i915/gt/intel_timeline.c

213

tl->fence_context, tl->hwsp_offset);

drivers/gpu/drm/i915/gt/intel_timeline.c

312

u32 next_ofs = offset_in_page(tl->hwsp_offset + TIMELINE_SEQNO_BYTES);

drivers/gpu/drm/i915/gt/intel_timeline.c

318

tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs;

drivers/gpu/drm/i915/gt/intel_timeline.c

62

u32 ofs = offset_in_page(timeline->hwsp_offset);

drivers/gpu/drm/i915/gt/intel_timeline.c

87

timeline->hwsp_offset = offset;

drivers/gpu/drm/i915/gt/intel_timeline.c

98

timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset;

drivers/gpu/drm/i915/gt/intel_timeline.h

83

u32 *hwsp_offset);

drivers/gpu/drm/i915/gt/intel_timeline_types.h

49

u32 hwsp_offset;

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

71

*cs++ = tl->hwsp_offset + slot * sizeof(u32);

drivers/gpu/drm/i915/gt/selftest_rc6.c

179

*cs++ = ce->timeline->hwsp_offset + 8;

drivers/gpu/drm/i915/gt/selftest_timeline.c

1392

tl->hwsp_offset, *tl->hwsp_seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

39

return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES;

drivers/gpu/drm/i915/gt/selftest_timeline.c

509

err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value);

drivers/gpu/drm/i915/gt/selftest_timeline.c

584

n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

654

n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);

drivers/gpu/drm/i915/gt/selftest_timeline.c

714

seqno[0], tl->hwsp_offset);

drivers/gpu/drm/i915/gt/selftest_timeline.c

716

err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]);

drivers/gpu/drm/i915/gt/selftest_timeline.c

731

seqno[1], tl->hwsp_offset);

drivers/gpu/drm/i915/gt/selftest_timeline.c

733

err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]);

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

5803

i915_request_active_timeline(rq)->hwsp_offset,

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

5879

i915_request_active_timeline(rq)->hwsp_offset,

drivers/gpu/drm/i915/i915_request.c

1150

u32 hwsp_offset;

drivers/gpu/drm/i915/i915_request.c

1158

err = intel_timeline_read_hwsp(from, to, &hwsp_offset);

drivers/gpu/drm/i915/i915_request.c

1184

*cs++ = hwsp_offset;

drivers/gpu/drm/i915/i915_request.h

697

page_mask_bits(i915_request_active_timeline(rq)->hwsp_offset);

drivers/gpu/drm/i915/selftests/i915_request.c

2017

const u32 offset = hwsp_offset(ce, sema);

drivers/gpu/drm/i915/selftests/i915_request.c

2092

const u32 offset = hwsp_offset(ce, sema);

drivers/gpu/drm/i915/selftests/i915_request.c

2163

const u32 offset = hwsp_offset(ce, sema);

drivers/gpu/drm/i915/selftests/i915_request.c

2266

const u32 offset = hwsp_offset(ce, sema);

drivers/gpu/drm/i915/selftests/i915_request.c

2357

const u32 offset = hwsp_offset(ce, sema);

drivers/gpu/drm/i915/selftests/i915_request.c

2451

const u32 offset = hwsp_offset(ce, sema);

drivers/gpu/drm/i915/selftests/i915_request.c

2571

const u32 offset = hwsp_offset(ce, sema);