hw_bank
struct hw_bank hw_bank;
return ioread32(ci->hw_bank.abs + offset) & mask;
data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
iowrite32(data, ci->hw_bank.abs + offset);
return ioread32(ci->hw_bank.regmap[reg]) & mask;
data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
__hw_write(ci, data, ci->hw_bank.regmap[reg]);
u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
__hw_write(ci, val, ci->hw_bank.regmap[reg]);
ci->hw_bank.regmap[i] =
(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
ci->hw_bank.regmap[i] = ci->hw_bank.op +
ci->hw_bank.phys = res->start;
enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
PORTSC_PHCD(ci->hw_bank.lpm));
hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
ci->hw_bank.abs = base;
ci->hw_bank.cap = ci->hw_bank.abs;
ci->hw_bank.cap += ci->platdata->capoffset;
ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
ci->hw_bank.lpm = reg;
ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
ci->hw_bank.size += OP_LAST;
ci->hw_bank.size /= sizeof(u32);
ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
if (ci->hw_bank.lpm) {
if (ci->hw_bank.lpm)
dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
hcd->rsrc_start = ci->hw_bank.phys;
hcd->rsrc_len = ci->hw_bank.size;
hcd->regs = ci->hw_bank.abs;
ehci->caps = ci->hw_bank.cap;
ehci->has_hostpc = ci->hw_bank.lpm;
ehci->has_tdi_phy_lpm = ci->hw_bank.lpm;
return ci->hw_bank.lpm ? hw_read(ci, OP_DEVLC, DEVLC_PSPD) :