CLK_AUDDIV_0
CLK_AUDDIV_0, 16, 1, CLK_AUDDIV_2, 0, 8, CLK_AUDDIV_0, 0),
CLK_AUDDIV_0, 17, 1, CLK_AUDDIV_2, 8, 8, CLK_AUDDIV_0, 1),
CLK_AUDDIV_0, 18, 1, CLK_AUDDIV_2, 16, 8, CLK_AUDDIV_0, 2),
CLK_AUDDIV_0, 19, 1, CLK_AUDDIV_2, 24, 8, CLK_AUDDIV_0, 3),
CLK_AUDDIV_0, 20, 1, CLK_AUDDIV_3, 0, 8, CLK_AUDDIV_0, 4),
CLK_AUDDIV_0, 21, 1, CLK_AUDDIV_3, 8, 8, CLK_AUDDIV_0, 5),
CLK_AUDDIV_0, 22, 1, CLK_AUDDIV_3, 16, 8, CLK_AUDDIV_0, 6),
CLK_AUDDIV_0, 23, 1, CLK_AUDDIV_3, 24, 8, CLK_AUDDIV_0, 7),
CLK_AUDDIV_0, 24, 1, CLK_AUDDIV_4, 0, 8, CLK_AUDDIV_0, 8),
CLK_AUDDIV_0, 25, 1, CLK_AUDDIV_4, 8, 8, CLK_AUDDIV_0, 9),
CLK_AUDDIV_0, 26, 1, CLK_AUDDIV_4, 16, 8, CLK_AUDDIV_0, 10),
CLK_AUDDIV_0, 27, 1, CLK_AUDDIV_4, 24, 8, CLK_AUDDIV_0, 11),
CLK_AUDDIV_0, 28, 1, CLK_AUDDIV_5, 0, 8, CLK_AUDDIV_0, 12),
apll_m_parents, CLK_AUDDIV_0, 29, 1),
"apll_tdmout_m", CLK_AUDDIV_0,
"apll_tdmout_m", CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,
.div_pdn_reg = CLK_AUDDIV_0,
.div_apll_sel_reg = CLK_AUDDIV_0,