arch/x86/hyperv/hv_crash.c

156

asm volatile("lgdt %0" : : "m" (hv_crash_ctxt.gdtr));

arch/x86/hyperv/hv_crash.c

160

:: "m"(hv_crash_ctxt.ss), "m"(hv_crash_ctxt.rsp));

arch/x86/hyperv/hv_crash.c

162

asm volatile("movw %0, %%ds" : : "m"(hv_crash_ctxt.ds));

arch/x86/hyperv/hv_crash.c

163

asm volatile("movw %0, %%es" : : "m"(hv_crash_ctxt.es));

arch/x86/hyperv/hv_crash.c

164

asm volatile("movw %0, %%fs" : : "m"(hv_crash_ctxt.fs));

arch/x86/hyperv/hv_crash.c

165

asm volatile("movw %0, %%gs" : : "m"(hv_crash_ctxt.gs));

arch/x86/hyperv/hv_crash.c

167

hv_wrmsr(MSR_IA32_CR_PAT, hv_crash_ctxt.pat);

arch/x86/hyperv/hv_crash.c

168

asm volatile("movq %0, %%cr0" : : "r"(hv_crash_ctxt.cr0));

arch/x86/hyperv/hv_crash.c

170

asm volatile("movq %0, %%cr8" : : "r"(hv_crash_ctxt.cr8));

arch/x86/hyperv/hv_crash.c

171

asm volatile("movq %0, %%cr4" : : "r"(hv_crash_ctxt.cr4));

arch/x86/hyperv/hv_crash.c

172

asm volatile("movq %0, %%cr2" : : "r"(hv_crash_ctxt.cr2));

arch/x86/hyperv/hv_crash.c

174

asm volatile("lidt %0" : : "m" (hv_crash_ctxt.idtr));

arch/x86/hyperv/hv_crash.c

175

hv_wrmsr(MSR_GS_BASE, hv_crash_ctxt.gsbase);

arch/x86/hyperv/hv_crash.c

176

hv_wrmsr(MSR_EFER, hv_crash_ctxt.efer);

arch/x86/hyperv/hv_crash.c

182

:: "r"(hv_crash_ctxt.cs), "r"(hv_crash_handle));

arch/x86/hyperv/hv_crash.c

200

struct hv_crash_ctxt *ctxt = &hv_crash_ctxt;

arch/x86/hyperv/hv_crash.c

80

static struct hv_crash_ctxt hv_crash_ctxt;