arch/mips/include/asm/octeon/cvmx-mio-defs.h

1113

uint64_t hs_timing:1;

arch/mips/include/asm/octeon/cvmx-mio-defs.h

1127

uint64_t hs_timing:1;

arch/mips/include/asm/octeon/cvmx-mio-defs.h

958

uint64_t hs_timing:1;

arch/mips/include/asm/octeon/cvmx-mio-defs.h

972

uint64_t hs_timing:1;

drivers/mmc/host/dw_mmc-k3.c

74

static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {

drivers/mmc/host/dw_mmc-pltfm.c

75

int i, rc, hs_timing;

drivers/mmc/host/dw_mmc-pltfm.c

93

hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift);

drivers/mmc/host/dw_mmc-pltfm.c

94

regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);