hfi1_cdbg
hfi1_cdbg(PROC, "PID %u %s affinity set to CPU set(s) %*pbl",
hfi1_cdbg(PROC, "CPUs used by interrupts: %*pbl",
hfi1_cdbg(PROC, "Same available HW thread on all physical CPUs: %*pbl",
hfi1_cdbg(PROC, "Device on NUMA %u, CPUs %*pbl", node,
hfi1_cdbg(PROC, "Available CPUs on NUMA %u: %*pbl", node,
hfi1_cdbg(PROC,
hfi1_cdbg(PROC, "Possible CPUs for process: %*pbl",
hfi1_cdbg(PROC, "Process assigned to CPU %d", cpu);
hfi1_cdbg(PROC, "Returning CPU %d for future process assignment", cpu);
hfi1_cdbg(AFFINITY,
hfi1_cdbg(AFFINITY,
hfi1_cdbg(AFFINITY,
hfi1_cdbg(PROC, "PID %u %s affinity set to CPU %*pbl",
hfi1_cdbg(LINKVERB, "SendContext[%d].SLID_CHECK = 0x%x",
hfi1_cdbg(RCVCTRL, "ctxt %d op 0x%x", ctxt, op);
hfi1_cdbg(RCVCTRL, "ctxt %d rcvctrl 0x%llx", ctxt, rcvctrl);
hfi1_cdbg(CNTR, "reading %s", entry->name);
hfi1_cdbg(CNTR, "\tDisabled");
hfi1_cdbg(CNTR, "\tPer VL");
hfi1_cdbg(
hfi1_cdbg(CNTR,
hfi1_cdbg(CNTR,
hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
hfi1_cdbg(CNTR, "reading %s", entry->name);
hfi1_cdbg(CNTR, "\tDisabled");
hfi1_cdbg(CNTR, "\tPer VL");
hfi1_cdbg(
hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
hfi1_cdbg(
hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
hfi1_cdbg(CNTR,
hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
hfi1_cdbg(DC8051, "type %d, data 0x%012llx", type, in_data);
hfi1_cdbg(PKT, "%s: packet dropped", __func__);
hfi1_cdbg(IOCTL, "IOCTL recv: 0x%x", cmd);
hfi1_cdbg(PROC,
hfi1_cdbg(PROC, "%u:%u Memory size mismatch %lu:%lu",
hfi1_cdbg(PROC, "closing ctxt %u:%u", uctxt->ctxt, fdata->subctxt);
hfi1_cdbg(PROC, "[%u:%u] pid %u assigned to CPU %d (NUMA %u)",
hfi1_cdbg(PROC, "allocated send context %u(%u)", uctxt->sc->sw_index,
hfi1_cdbg(FIRMWARE, "Firmware %s details:", name);
hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size);
hfi1_cdbg(FIRMWARE, "CSS structure:");
hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type);
hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)",
hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version);
hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id);
hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor);
hfi1_cdbg(FIRMWARE, " date 0x%x", css->date);
hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)",
hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)",
hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)",
hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)",
hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes",
hfi1_cdbg(PROC,
hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u",
hfi1_cdbg(PROC,
hfi1_cdbg(PROC, "setting up context %u", rcd->ctxt);
hfi1_cdbg(PROC,
hfi1_cdbg(PROC,
hfi1_cdbg(PIO,
hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
hfi1_cdbg(DEBUG, fmt, ##__VA_ARGS__)
hfi1_cdbg(TID,
hfi1_cdbg(TID,
hfi1_cdbg(TID, "total mapped: tidpairs:%u pages:%u (%d)", tididx,
hfi1_cdbg(TID, "Failed to unprogram rcv array %d",
hfi1_cdbg(TID, "Failed to insert RB node %u 0x%lx, 0x%lx %d",
hfi1_cdbg(
hfi1_cdbg(SDMA, "[%u:%u:%u] Failed to copy info QW (%d)",
hfi1_cdbg(SDMA,
hfi1_cdbg(SDMA,
hfi1_cdbg(SDMA,
hfi1_cdbg(SDMA, "[%u:%u:%u] Entry %u is in use",
hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \
hfi1_cdbg(
hfi1_cdbg(PIO, "alloc failed. state active, queuing");
hfi1_cdbg(PIO, "%s() Failed. Completing with err",