Symbol: hpd_pin
drivers/gpu/drm/bridge/tc358767.c
1775
conn = val & BIT(tc->hpd_pin);
drivers/gpu/drm/bridge/tc358767.c
1788
if (tc->hpd_pin >= 0)
drivers/gpu/drm/bridge/tc358767.c
1851
if (tc->hpd_pin >= 0) {
drivers/gpu/drm/bridge/tc358767.c
2248
if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) {
drivers/gpu/drm/bridge/tc358767.c
2255
bool h = val & INT_GPIO_H(tc->hpd_pin);
drivers/gpu/drm/bridge/tc358767.c
2256
bool lc = val & INT_GPIO_LC(tc->hpd_pin);
drivers/gpu/drm/bridge/tc358767.c
2259
dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
drivers/gpu/drm/bridge/tc358767.c
2371
if (tc->hpd_pin >= 0)
drivers/gpu/drm/bridge/tc358767.c
2513
&tc->hpd_pin);
drivers/gpu/drm/bridge/tc358767.c
2515
tc->hpd_pin = -ENODEV;
drivers/gpu/drm/bridge/tc358767.c
2517
if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
drivers/gpu/drm/bridge/tc358767.c
2568
if (tc->hpd_pin >= 0) {
drivers/gpu/drm/bridge/tc358767.c
2569
u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
drivers/gpu/drm/bridge/tc358767.c
2570
u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
drivers/gpu/drm/bridge/tc358767.c
2576
regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
drivers/gpu/drm/bridge/tc358767.c
399
int hpd_pin;
drivers/gpu/drm/i915/display/g4x_dp.c
1190
u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/g4x_dp.c
1200
switch (encoder->hpd_pin) {
drivers/gpu/drm/i915/display/g4x_dp.c
1211
MISSING_CASE(encoder->hpd_pin);
drivers/gpu/drm/i915/display/g4x_dp.c
1221
u32 bit = display->hotplug.hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/g4x_dp.c
1397
intel_encoder->hpd_pin = intel_hpd_pin_default(port);
drivers/gpu/drm/i915/display/g4x_hdmi.c
753
intel_encoder->hpd_pin = intel_hpd_pin_default(port);
drivers/gpu/drm/i915/display/intel_crt.c
1078
crt->base.hpd_pin = HPD_CRT;
drivers/gpu/drm/i915/display/intel_ddi.c
4886
u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_ddi.c
4894
u32 bit = display->hotplug.hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_ddi.c
4902
u32 bit = display->hotplug.hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_ddi.c
4983
static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
4993
static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5001
static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5009
static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5020
static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5028
static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5039
static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port)
drivers/gpu/drm/i915/display/intel_ddi.c
5395
encoder->hpd_pin = xelpd_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5397
encoder->hpd_pin = dg1_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5399
encoder->hpd_pin = rkl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5401
encoder->hpd_pin = tgl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5403
encoder->hpd_pin = ehl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5405
encoder->hpd_pin = icl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5407
encoder->hpd_pin = skl_hpd_pin(display, port);
drivers/gpu/drm/i915/display/intel_ddi.c
5409
encoder->hpd_pin = intel_hpd_pin_default(port);
drivers/gpu/drm/i915/display/intel_display_regs.h
1297
#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
drivers/gpu/drm/i915/display/intel_display_regs.h
1298
#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
drivers/gpu/drm/i915/display/intel_display_regs.h
1313
#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1366
#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1373
#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1387
#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1388
#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1389
#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1390
#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1396
#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1398
#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1400
#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1402
#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1409
#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
drivers/gpu/drm/i915/display/intel_display_regs.h
1674
#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1675
#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
drivers/gpu/drm/i915/display/intel_display_regs.h
1676
#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
drivers/gpu/drm/i915/display/intel_display_regs.h
1752
#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1753
#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1754
#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1755
#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1756
#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1757
#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1758
#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1761
#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1762
#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_regs.h
1763
#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
drivers/gpu/drm/i915/display/intel_display_types.h
295
enum hpd_pin hpd_pin;
drivers/gpu/drm/i915/display/intel_dp.c
6535
unsigned int hpd_pin = encoder->hpd_pin;
drivers/gpu/drm/i915/display/intel_dp.c
6539
if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
drivers/gpu/drm/i915/display/intel_dp.c
6540
display->hotplug.event_bits |= BIT(hpd_pin);
drivers/gpu/drm/i915/display/intel_dp.c
6542
__assign_bit(hpd_pin,
drivers/gpu/drm/i915/display/intel_hotplug.c
1025
static bool block_hpd_pin(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
1036
static bool unblock_hpd_pin(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
1080
if (encoder->hpd_pin == HPD_NONE)
drivers/gpu/drm/i915/display/intel_hotplug.c
1085
if (block_hpd_pin(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
109
static enum hpd_pin
drivers/gpu/drm/i915/display/intel_hotplug.c
1090
if (do_flush && hpd_pin_has_pulse(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
1107
if (encoder->hpd_pin == HPD_NONE)
drivers/gpu/drm/i915/display/intel_hotplug.c
1112
if (unblock_hpd_pin(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
1130
enum hpd_pin pin = encoder->hpd_pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
120
return encoder ? encoder->hpd_pin : HPD_NONE;
drivers/gpu/drm/i915/display/intel_hotplug.c
153
enum hpd_pin pin, bool long_hpd)
drivers/gpu/drm/i915/display/intel_hotplug.c
238
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
276
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
355
static bool hpd_pin_has_pulse(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
360
if (encoder->hpd_pin != pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
370
static bool hpd_pin_is_blocked(struct intel_display *display, enum hpd_pin pin)
drivers/gpu/drm/i915/display/intel_hotplug.c
379
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
412
enum hpd_pin pin = encoder->hpd_pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
458
hotplug->short_hpd_pin_mask |= BIT(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug.c
459
if (!hpd_pin_is_blocked(display, encoder->hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug.c
507
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
595
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
611
pin = encoder->hpd_pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
812
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug.c
97
enum hpd_pin intel_hpd_pin_default(enum port port)
drivers/gpu/drm/i915/display/intel_hotplug.c
997
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug.h
28
enum hpd_pin intel_hpd_pin_default(enum port port);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1013
mtp_ddi_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1029
mtp_tc_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1089
static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1091
return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1095
enum hpd_pin hpd_pin, bool enable)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1100
if (!is_xelpdp_pica_hpd_pin(hpd_pin))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1103
intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1111
_xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1118
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1123
available_pins |= BIT(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1154
static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1156
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1172
return spt_hotplug_mask(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1175
static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1177
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1187
return spt_hotplug2_mask(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1220
spt_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1224
spt_hotplug2_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1243
static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1245
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1256
switch (encoder->hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1282
ilk_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1305
static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1307
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1323
switch (encoder->hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1356
bxt_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
1385
u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
19
typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
21
typedef u32 (*hotplug_mask_func)(enum hpd_pin pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
216
static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
231
static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
245
static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
258
static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
273
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
283
static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
299
static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
309
static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
323
static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
348
bool long_pulse_detect(enum hpd_pin pin, u32 val))
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
350
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
376
if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
377
enabled_irqs |= hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
389
hotplug_irqs |= hpd[encoder->hpd_pin];
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
397
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
520
enum hpd_pin pin;
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
693
static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
695
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
713
switch (encoder->hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
752
ibx_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
768
static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
770
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
775
return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
783
return icp_ddi_hotplug_mask(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
786
static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
788
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
795
return ICP_TC_HPD_ENABLE(hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
803
return icp_tc_hotplug_mask(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
818
icp_ddi_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
834
icp_tc_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
863
static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
865
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
872
return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
880
return gen11_hotplug_mask(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
918
gen11_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
934
gen11_hotplug_mask(encoder->hpd_pin),
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
967
static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
969
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
972
return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
980
return mtp_ddi_hotplug_mask(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
983
static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
985
switch (hpd_pin) {
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
990
return ICP_TC_HPD_ENABLE(hpd_pin);
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
998
return mtp_tc_hotplug_mask(encoder->hpd_pin);
drivers/gpu/drm/i915/display/intel_sdvo.c
3467
intel_encoder->hpd_pin = HPD_SDVO_B;
drivers/gpu/drm/i915/display/intel_sdvo.c
3469
intel_encoder->hpd_pin = HPD_SDVO_C;
drivers/gpu/drm/i915/display/intel_tc.c
1010
enum hpd_pin hpd_pin = dig_port->base.hpd_pin;
drivers/gpu/drm/i915/display/intel_tc.c
1011
u32 pica_isr_bits = display->hotplug.hpd[hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
1012
u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
527
u32 isr_bit = display->hotplug.pch_hpd[dig_port->base.hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
815
enum hpd_pin hpd_pin = dig_port->base.hpd_pin;
drivers/gpu/drm/i915/display/intel_tc.c
816
u32 cpu_isr_bits = display->hotplug.hpd[hpd_pin];
drivers/gpu/drm/i915/display/intel_tc.c
817
u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin];