drivers/gpu/host1x/dev.h

185

void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r);

drivers/gpu/host1x/hw/cdma_hw.c

100

host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,

drivers/gpu/host1x/hw/cdma_hw.c

107

host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART);

drivers/gpu/host1x/hw/cdma_hw.c

109

host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI);

drivers/gpu/host1x/hw/cdma_hw.c

111

host1x_ch_writel(ch, lower_32_bits(end), HOST1X_CHANNEL_DMAEND);

drivers/gpu/host1x/hw/cdma_hw.c

113

host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI);

drivers/gpu/host1x/hw/cdma_hw.c

117

host1x_ch_writel(ch, getptr, HOST1X_CHANNEL_DMAPUT);

drivers/gpu/host1x/hw/cdma_hw.c

118

host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP |

drivers/gpu/host1x/hw/cdma_hw.c

130

host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,

drivers/gpu/host1x/hw/cdma_hw.c

132

host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT);

drivers/gpu/host1x/hw/cdma_hw.c

135

host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMACTRL);

drivers/gpu/host1x/hw/cdma_hw.c

148

host1x_ch_writel(ch, cdma->push_buffer.pos,

drivers/gpu/host1x/hw/cdma_hw.c

162

host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,

drivers/gpu/host1x/hw/cdma_hw.c

174

host1x_ch_writel(ch, stop ? 0x1 : 0x0, HOST1X_CHANNEL_CMDPROC_STOP);

drivers/gpu/host1x/hw/cdma_hw.c

188

host1x_ch_writel(ch, 0x1, HOST1X_CHANNEL_TEARDOWN);

drivers/gpu/host1x/hw/cdma_hw.c

217

host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,

drivers/gpu/host1x/hw/cdma_hw.c

55

host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP,

drivers/gpu/host1x/hw/cdma_hw.c

59

host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART);

drivers/gpu/host1x/hw/cdma_hw.c

61

host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI);

drivers/gpu/host1x/hw/cdma_hw.c

63

host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT);

drivers/gpu/host1x/hw/cdma_hw.c

65

host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMAPUT_HI);

drivers/gpu/host1x/hw/cdma_hw.c

67

host1x_ch_writel(ch, lower_32_bits(end), HOST1X_CHANNEL_DMAEND);

drivers/gpu/host1x/hw/cdma_hw.c

69

host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI);

drivers/gpu/host1x/hw/cdma_hw.c

73

host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP |

drivers/gpu/host1x/hw/cdma_hw.c

79

host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMACTRL);

drivers/gpu/host1x/hw/channel_hw.c

185

host1x_ch_writel(channel, stream_id, HOST1X_CHANNEL_SMMU_STREAMID);

drivers/gpu/host1x/hw/channel_hw.c

204

host1x_ch_writel(ch,