hclge_read_dev
hclge_read_dev(&hdev->hw, offset));
hclge_read_dev(&hdev->hw, offset));
reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
hw_err_src_flag = hclge_read_dev(&hdev->hw,
cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
hw_err_src_reg = hclge_read_dev(&hdev->hw,
val = hclge_read_dev(&hdev->hw, reg);
val = hclge_read_dev(&hdev->hw, reg);
reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING),
hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
} else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
int tail = hclge_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG);
*reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
*reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
*reg++ = hclge_read_dev(&hdev->hw,