hbg_reg_read
if (hbg_reg_read(priv, HBG_REG_PUSH_REQ_ADDR) != 1)
info->val = hbg_reg_read(priv, info->offset);
hbg_reg_read(priv, stats->reg));
hbg_reg_read(priv, HBG_REG_CF_IND_TXINT_STAT_ADDR));
hbg_reg_read(priv, HBG_REG_CF_IND_RXINT_STAT_ADDR));
return hbg_reg_read(priv, HBG_REG_CF_IND_TXINT_MSK_ADDR);
return hbg_reg_read(priv, HBG_REG_CF_IND_RXINT_MSK_ADDR);
return hbg_reg_read(priv, HBG_REG_CF_INTRPT_MSK_ADDR) & mask;
value = hbg_reg_read(priv, HBG_REG_CF_INTRPT_MSK_ADDR);
value = hbg_reg_read(priv, HBG_REG_CFG_FIFO_THRSLD_ADDR);
return hbg_reg_read(priv, HBG_REG_SPEC_VALID_ADDR) &&
!hbg_reg_read(priv, HBG_REG_EVENT_REQ_ADDR);
specs->mac_id = hbg_reg_read(priv, HBG_REG_MAC_ID_ADDR);
specs->phy_addr = hbg_reg_read(priv, HBG_REG_PHY_ID_ADDR);
specs->mdio_frequency = hbg_reg_read(priv, HBG_REG_MDIO_FREQ_ADDR);
specs->max_mtu = hbg_reg_read(priv, HBG_REG_MAX_MTU_ADDR);
specs->min_mtu = hbg_reg_read(priv, HBG_REG_MIN_MTU_ADDR);
specs->vlan_layers = hbg_reg_read(priv, HBG_REG_VLAN_LAYERS_ADDR);
specs->rx_fifo_num = hbg_reg_read(priv, HBG_REG_RX_FIFO_NUM_ADDR);
specs->tx_fifo_num = hbg_reg_read(priv, HBG_REG_TX_FIFO_NUM_ADDR);
specs->uc_mac_num = hbg_reg_read(priv, HBG_REG_UC_MAC_NUM_ADDR);
status = hbg_reg_read(priv, HBG_REG_CF_INTRPT_STAT_ADDR);
FIELD_GET(mask, hbg_reg_read(priv, addr))
u32 _value = hbg_reg_read(_priv, _addr); \
*cmd = hbg_reg_read(HBG_MAC_GET_PRIV(mac), HBG_REG_MDIO_COMMAND_ADDR);