hinic3_hwif_write_reg
hinic3_hwif_write_reg(eq->hwdev->hwif, addr, val);
hinic3_hwif_write_reg(hwif, HINIC3_CSR_AEQ_CTRL_0_ADDR, ctrl0);
hinic3_hwif_write_reg(hwif, HINIC3_CSR_AEQ_CTRL_1_ADDR, ctrl1);
hinic3_hwif_write_reg(hwif, reg, upper_32_bits(page_paddr));
hinic3_hwif_write_reg(hwif, reg, lower_32_bits(page_paddr));
hinic3_hwif_write_reg(eq->hwdev->hwif,
hinic3_hwif_write_reg(eq->hwdev->hwif, EQ_PROD_IDX_REG_ADDR(eq), 0);
hinic3_hwif_write_reg(hwdev->hwif, HINIC3_EQ_INDIR_IDX_ADDR(eq->type),
hinic3_hwif_write_reg(eq->hwdev->hwif,
hinic3_hwif_write_reg(eq->hwdev->hwif,
hinic3_hwif_write_reg(hwdev->hwif, addr, val);
hinic3_hwif_write_reg(hwif, addr, attr4);
hinic3_hwif_write_reg(hwif, addr, val);
hinic3_hwif_write_reg(hwif, addr, mask_bits);
hinic3_hwif_write_reg(hwif, addr, msix_ctrl);
hinic3_hwif_write_reg(hwif, addr, mask_bits);
hinic3_hwif_write_reg(hwif, HINIC3_CSR_FUNC_ATTR6_ADDR, attr6);
void hinic3_hwif_write_reg(struct hinic3_hwif *hwif, u32 reg, u32 val);
hinic3_hwif_write_reg(mbox->hwdev->hwif, MBOX_MQ_CI_OFFSET, val);
hinic3_hwif_write_reg(hwdev->hwif, HINIC3_FUNC_CSR_MAILBOX_RESULT_H_OFF,
hinic3_hwif_write_reg(hwdev->hwif, HINIC3_FUNC_CSR_MAILBOX_RESULT_L_OFF,
hinic3_hwif_write_reg(hwdev->hwif, HINIC3_FUNC_CSR_MAILBOX_RESULT_H_OFF,
hinic3_hwif_write_reg(hwdev->hwif, HINIC3_FUNC_CSR_MAILBOX_RESULT_L_OFF,
hinic3_hwif_write_reg(hwif, HINIC3_FUNC_CSR_MAILBOX_INT_OFF, mbox_int);
hinic3_hwif_write_reg(hwif, HINIC3_FUNC_CSR_MAILBOX_CONTROL_OFF,