hifn_write_1
hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
hifn_write_1(dev, HIFN_1_DMA_CSR, r);
hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
hifn_write_1(dev, HIFN_1_PUB_STATUS,
hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
hifn_write_1(dev, HIFN_1_DMA_CSR,
hifn_write_1(dev, HIFN_1_DMA_IER, 0);
hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
hifn_write_1(dev, HIFN_1_RNG_CONFIG,
hifn_write_1(dev, HIFN_1_DMA_CNFG,
hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
hifn_write_1(dev, HIFN_1_PLL, pllcfg |
hifn_write_1(dev, HIFN_1_PLL, pllcfg |
hifn_write_1(dev, HIFN_1_PLL, pllcfg |
hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
hifn_write_1(dev, HIFN_1_DMA_CSR,
hifn_write_1(dev, HIFN_1_DMA_CSR,