hideep_pgm_w_reg
hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \
hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03); \
hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, \
hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);