CLK_48
D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),
D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),
D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),
D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),
D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),
if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
__func__, clk_name, CLK_44, CLK_48);
if (req->rate != CLK_48 && req->rate != CLK_44) {
__func__, clk_name, CLK_44, CLK_48);
req->rate = CLK_48;
if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
__func__, clk_name, CLK_44, CLK_48);
if (req->rate != CLK_48 && req->rate != CLK_44) {
__func__, clk_name, CLK_44, CLK_48);
req->rate = CLK_48;
rt5682s->lrck[RT5682S_AIF1] = CLK_48;