drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

145

hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_REQ, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

158

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_SEL, 0x0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

159

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIMEOUT, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

160

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE_NUM,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

23

hibmc_dp_reg_write_field(dp, HIBMC_DP_DPTX_RST_CTRL, HIBMC_DP_CFG_AUX_RST_N, 0x0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c

25

hibmc_dp_reg_write_field(dp, HIBMC_DP_DPTX_RST_CTRL, HIBMC_DP_CFG_AUX_RST_N, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

100

hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG2,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

102

hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG3,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

106

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG0,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

108

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG0,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

110

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG2,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

114

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG1,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

116

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG1,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

118

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG3,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

121

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CONFIG3,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

125

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_MSA0,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

127

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_MSA0,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

130

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_VSYNC_POLARITY,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

132

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_HSYNC_POLARITY,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

141

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_RGB_ENABLE, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

142

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_VIDEO_MAPPING, 0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

148

hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_MODEL_CTRL,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

217

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_SEL, 0x0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

218

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIMEOUT, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

219

hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE_NUM, 0x9);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

233

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_VIDEO_CTRL, BIT(0), 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

235

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_DPTX_GCTL0, BIT(10), 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

238

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_DPTX_GCTL0, BIT(10), 0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

240

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_VIDEO_CTRL, BIT(0), 0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

301

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(9),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

303

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, GENMASK(8, 1),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

306

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(10), 0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

311

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(10), 1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

312

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, GENMASK(23, 12),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

314

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL1, GENMASK(23, 12),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

316

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL1, GENMASK(11, 0),

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

321

hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(0), cfg->enable);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

42

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

44

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

72

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_HORIZONTAL_SIZE,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

74

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_HORIZONTAL_SIZE,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

76

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

93

hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG0,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

95

hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG0,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c

98

hibmc_dp_reg_write_field(dp, HIBMC_DP_TIMING_GEN_CONFIG2,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

34

hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_LANE_DATA_EN,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

36

hibmc_dp_reg_write_field(dp, HIBMC_DP_DPTX_GCTL0, HIBMC_DP_CFG_PHY_LANE_NUM,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

40

hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_FRAME_MODE, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

72

hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_SCRAMBLE_EN, 0x1);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

74

hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_SCRAMBLE_EN, 0);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

97

hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_PAT_SEL, val);