arch/arm/mach-spear/time.c

75

writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));

arch/arm/mach-spear/time.c

81

writew(0xFFFF, gpt_base + LOAD(CLKSRC));

arch/arm/mach-spear/time.c

83

val = readw(gpt_base + CR(CLKSRC));

arch/arm/mach-spear/time.c

86

writew(val, gpt_base + CR(CLKSRC));

arch/arm/mach-spear/time.c

89

clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,

drivers/mmc/host/dw_mmc.c

1253

mci_writel(host, CLKSRC, 0);

drivers/mmc/host/dw_mmc.c

3519

mci_writel(host, CLKSRC, 0);

drivers/mmc/host/dw_mmc.c

3594

mci_writel(host, CLKSRC, 0);