CLKSEL
{"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
{"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
{"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
{"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
{"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
{"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
{"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
{"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
{"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
{"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID},
{"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1},
{"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1},
CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, M10V_UHS1CLK2_ID},
CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10)))
write_valid_reg = base + CLKSEL(11);
base + CLKSEL(1), 0, 3, 0, rclk_table,
return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
clksel = mci_readl(host, CLKSEL);
mci_writel(host, CLKSEL, clksel);
clksel = mci_readl(host, CLKSEL);
mci_writel(host, CLKSEL, clksel);
return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
clksel = mci_readl(host, CLKSEL);
mci_writel(host, CLKSEL, clksel);
clksel = mci_readl(host, CLKSEL);
mci_writel(host, CLKSEL, clksel);
val &= CLKSEL;
val |= FIELD_PREP(CLKSEL, CLKSEL_24M);