drivers/clk/ux500/reset-prcc.c

40

return CLKRST1_INDEX;

drivers/clk/ux500/u8500_of_clk.c

303

clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

307

clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

311

clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

315

clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

319

clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

323

clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

327

clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

331

clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

335

clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

339

clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

343

clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

347

clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],

drivers/clk/ux500/u8500_of_clk.c

489

bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

493

bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

497

bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

501

bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

505

bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

509

bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

513

bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

517

bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

521

bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);

drivers/clk/ux500/u8500_of_clk.c

525

bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);