drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2995

struct gsl_params *gsl = &params->tg_set_gsl_params.gsl;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4210

struct gsl_params gsl)

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1221

const struct dcp_gsl_params *gsl_params)

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1237

gsl_params->gsl_master == tg->inst,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

1257

gsl_params->gsl_master,

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h

171

const struct dcp_gsl_params *gsl_params);

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

628

const struct dcp_gsl_params *gsl_params)

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

630

(void)gsl_params;

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

247

const struct dcp_gsl_params *gsl_params)

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

266

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2917

struct dcp_gsl_params gsl_params = { 0 };

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2926

gsl_params.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2927

gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2931

grouped_pipes[i]->stream_res.tg, &gsl_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2939

gsl_params.gsl_group);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2962

struct dcp_gsl_params gsl_params = { 0 };

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2966

gsl_params.gsl_group = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2967

gsl_params.gsl_master = 0;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2971

grouped_pipes[i]->stream_res.tg, &gsl_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2978

gsl_params.gsl_master,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

224

struct gsl_params gsl;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

227

memset(&gsl, 0, sizeof(struct gsl_params));

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3463

struct gsl_params gsl;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3466

memset(&gsl, 0, sizeof(struct gsl_params));

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2130

struct gsl_params gsl);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

319

struct gsl_params gsl;

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

396

const struct dcp_gsl_params *gsl_params);

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

490

void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

87

const struct gsl_params *params)

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h

95

const struct gsl_params *params);